Closed tcbennun closed 6 months ago
Tested with ADC1 on H503. The ClockMux::adcdacsel
field plus init code is generated correctly in embassy-stm32.
thanks!
(the u5 exception is a bit unfortunate, but perhaps it's our "fault" because all HCLKs are the same freq (almost always :smiling_face_with_tear:) , so perhaps we should be using HCLK instead of HCLK1/HCLK2/etc.)
thanks!
(the u5 exception is a bit unfortunate, but perhaps it's our "fault" because all HCLKs are the same freq (almost always 🥲) , so perhaps we should be using HCLK instead of HCLK1/HCLK2/etc.)
yeah; for APB periphs it makes sense as you have a prescaler per APB clock, but AFAIK all AHBs will share the same prescaler... do you know some exceptions to this?
edit: literally just found an exception in the WBA series, so, yeah...
stm32wl/stm32wb have separate prescalers for core2_ahb, shared_ahb. stm32wba has a separate prescaler for ahb5.
the clock selection bit is named ADCDACSEL, shared between all ADCs and DACs