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embassy-rs / stm32-data

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fix ADC, DAC clock muxes for H5, U5 #433

Closed tcbennun closed 6 months ago

tcbennun commented 6 months ago

the clock selection bit is named ADCDACSEL, shared between all ADCs and DACs

embassy-ci[bot] commented 6 months ago

diff: https://ci.embassy.dev/jobs/e75353b49de4/artifacts/diff.html

tcbennun commented 6 months ago

Tested with ADC1 on H503. The ClockMux::adcdacsel field plus init code is generated correctly in embassy-stm32.

Dirbaio commented 6 months ago

thanks!

(the u5 exception is a bit unfortunate, but perhaps it's our "fault" because all HCLKs are the same freq (almost always :smiling_face_with_tear:) , so perhaps we should be using HCLK instead of HCLK1/HCLK2/etc.)

tcbennun commented 6 months ago

thanks!

(the u5 exception is a bit unfortunate, but perhaps it's our "fault" because all HCLKs are the same freq (almost always 🥲) , so perhaps we should be using HCLK instead of HCLK1/HCLK2/etc.)

yeah; for APB periphs it makes sense as you have a prescaler per APB clock, but AFAIK all AHBs will share the same prescaler... do you know some exceptions to this?

edit: literally just found an exception in the WBA series, so, yeah...

Dirbaio commented 6 months ago

stm32wl/stm32wb have separate prescalers for core2_ahb, shared_ahb. stm32wba has a separate prescaler for ahb5.