Add support for HSEM

[taunusflieger]

Add support for the hardware semaphore

The main issue with implementing HSEM is that the Cube XML is missing HSEM information except for the wle5. Without the Cube XML information the data generation process will not generate the data for HSEM. Therefore a preliminary patch has been implemented in chips.rs (see also https://github.com/embassy-rs/stm32-data/issues/444). I'm unsure about the implemented patch - would appriciate feedback.

chips with HSEM h745 h747 h755 h757 h735 h7b3 h753v h753 h743 h743v mp157 mp153 wb55 wba52 wl5x_cm0p wl5x_cm4 wle5

The current draft PR contains the HSEM implementation for:

h745 h747 h755 h757 wle5

[embassy-ci[bot]]

diff: https://ci.embassy.dev/jobs/51e8000d683f/artifacts/diff.html

[taunusflieger]

Hey @Dirbaio would appreciate your input here

[embassy-ci[bot]]

diff: https://ci.embassy.dev/jobs/6b15c565cff4/artifacts/diff.html

[Dirbaio]

We already have GHOST_PERIS for handling peripherals that are missing in cubedb, can you add HSEM there instead of adding custom code?

Also, there's no way there's 8 versions. from looking at the RMs, there's:

• h7 singlecore: 32 semaphores, 1 irq line.
• h7 multicore: 32 semaphores, 2 irq lines (one per core)
• wb: 32 semaphores, 2 irq lines (one per core)
• wba: 16 semaphores, trustzone shit (LOCK, PRIV bits, secure and nonsecure irq lines)
• wl5: 16 semaphores, 2 irq lines (one per core)
• wle: 16 semaphores, 1 irq line

H7 multicore and WB are the same, so this is 5 versions in total.

Can you rearrange versions to match that? the preivous PR #215 was quite close.

also, please make sure to cleanup the yamls (convert stuff to arrays, remove dupe enums, remove useless single-bot enums...), and minimize the diff between versions for easy review.

[embassy-ci[bot]]

diff: https://ci.embassy.dev/jobs/dfb26b709753/artifacts/diff.html

[embassy-ci[bot]]

diff: https://ci.embassy.dev/jobs/54f518e21344/artifacts/diff.html

[taunusflieger]

The following list shows the different hsem yaml versions and the corresponding chips. wba is on purpose not included at is complex and very different from the others which will also make the HSEM implementation in the HAL more complex. I leave this out for another PR.

v1:

• h747
• wb55

v2:

• h735
• h7b3
• h753v
• h753
• h743
• h743v

v3:

• wl5x_cm0p
• wl5x_cm4

v4:

• wle5

[Dirbaio]

• in v1,v2 coreid is 4 bits, not 8bits. in CR, R, RLR.
• To make it easier to make the HAL to work on all chips, you might want to unify the registers more. Up to you, though. Here are some ideas:
  • rename "MASTERID" to "COREID"
  • Make the interrupt registers an array, so you can index it by core number (0 or 1) instead of doing a match and copypasting the register access 2 times.
  • Always make the interrupt registers an array, just make it length 1 or 2 depending on the chip. so you don't need two versions, one for multicore and another for singlecore. Same code for singlecore works except you make the index always 0.

[embassy-ci[bot]]

diff: https://ci.embassy.dev/jobs/36827e05b690/artifacts/diff.html

[embassy-ci[bot]]

diff: https://ci.embassy.dev/jobs/60a0ade3c82c/artifacts/diff.html

[Dirbaio]

@taunusflieger please check the diff the CI is posting, it's not appearing for H7 chips.

[embassy-ci[bot]]

diff: https://ci.embassy.dev/jobs/b4d4bb248aba/artifacts/diff.html

[embassy-ci[bot]]

diff: https://ci.embassy.dev/jobs/bb6bd18b2716/artifacts/diff.html