Fix ADC resolution enum for stm32g4

[qff233]

Such as #440 and #448. ADC resolution enum is error. I get the resolution bit from LL. Here is the resolution bit in LL.

#define LL_ADC_RESOLUTION_12B              (0x00000000UL)                      /*!< ADC resolution 12 bits */
#define LL_ADC_RESOLUTION_10B              (                 ADC_CFGR_RES_0)   /*!< ADC resolution 10 bits */
#define LL_ADC_RESOLUTION_8B               (ADC_CFGR_RES_1                 )   /*!< ADC resolution  8 bits */
#define LL_ADC_RESOLUTION_6B               (ADC_CFGR_RES_1 | ADC_CFGR_RES_0)   /*!< ADC resolution  6 bits */

So I copy from adc_v4 to adc_g4. And I change the ADC resolution enum.

[embassy-ci[bot]]

diff: https://ci.embassy.dev/jobs/b730e2e578b7/artifacts/diff.html

[embassy-ci[bot]]

diff: https://ci.embassy.dev/jobs/5b3848b18fd1/artifacts/diff.html

[qff233]

And I find the ADC sample_time enum is error alse. So I change it. Here is the sample_time in LL.

/**
  * @}
  */

/** @defgroup ADC_LL_EC_CHANNEL_SAMPLINGTIME  Channel - Sampling time
  * @{
  */
#define LL_ADC_SAMPLINGTIME_2CYCLES_5      (0x00000000UL)       /*!< Sampling time 2.5 ADC clock cycles */
#define LL_ADC_SAMPLINGTIME_6CYCLES_5      (ADC_SMPR2_SMP10_0)  /*!< Sampling time 6.5 ADC clock cycles */
#define LL_ADC_SAMPLINGTIME_12CYCLES_5     (ADC_SMPR2_SMP10_1)  /*!< Sampling time 12.5 ADC clock cycles */
#define LL_ADC_SAMPLINGTIME_24CYCLES_5     (ADC_SMPR2_SMP10_1 | ADC_SMPR2_SMP10_0) /*!< Sampling time 24.5 ADC clock cycles */
#define LL_ADC_SAMPLINGTIME_47CYCLES_5     (ADC_SMPR2_SMP10_2)  /*!< Sampling time 47.5 ADC clock cycles */
#define LL_ADC_SAMPLINGTIME_92CYCLES_5     (ADC_SMPR2_SMP10_2 \
                                            | ADC_SMPR2_SMP10_0) /*!< Sampling time 92.5 ADC clock cycles */
#define LL_ADC_SAMPLINGTIME_247CYCLES_5    (ADC_SMPR2_SMP10_2 \
                                            | ADC_SMPR2_SMP10_1) /*!< Sampling time 247.5 ADC clock cycles */
#define LL_ADC_SAMPLINGTIME_640CYCLES_5    (ADC_SMPR2_SMP10_2 \
                                            | ADC_SMPR2_SMP10_1 \
                                            | ADC_SMPR2_SMP10_0) /*!< Sampling time 640.5 ADC clock cycles */

[embassy-ci[bot]]

diff: https://ci.embassy.dev/jobs/ab4fa38da3de/artifacts/diff.html

[embassy-ci[bot]]

diff: https://ci.embassy.dev/jobs/6689ac54a060/artifacts/diff.html

[Dirbaio]

RES on G4 is actually on bit_offset 3 and has bit_size 2.

[qff233]

Oh! I want to fix it. please wait a while. Now, I check it with datasheet.

[embassy-ci[bot]]

diff: https://ci.embassy.dev/jobs/3931ee566611/artifacts/diff.html

[qff233]

Hey,I calibration the adc register for stm32g4 serial. It is different from other chip using adc_v4.