rework on LPTIM

[eZioPan]

This is a full rework on LPTIM on entire STM32.

Here is the relationship between versions:

lptim_v1 -> l0 lptim_v1a = lptim_v1 + LPTIM_OR -> f4, f7, l4 lptim_v1b = lptim_v1a + LPTIM_CR_COUNTRST + LPTIM_CR_RSTARE -> g0, l4+(pqrs), wb lptim_v1b_g4 = lptim_v1b with discontinuous LPTIM_CFGR_TIGSEL -> g4 lptim_v1b_h7 = lptim_v1b without LPTIM_OR, with LPTIM_CFGR2 lptim_v1c = lptim_v1b + LPTIM_ISR_UE + LPTIM_ISR_REPOK + LPTIM_RCR -> l5, wl lptim_v2a -> h5, u5, wba lptim_v2b -> u0

The actual data is created in a reversed order (v2 -> v1c -> v1b_h7 -> v1b_g4 -> v1b -> v1a -> v1), and description is copied from v2. Thus description might not reflect the actual description for all v1(s) data.

[embassy-ci[bot]]

diff: https://ci.embassy.dev/jobs/d3d2eebb0ad2/artifacts/diff.html

[embassy-ci[bot]]

diff: https://ci.embassy.dev/jobs/0364b88b0de3/artifacts/diff.html

[embassy-ci[bot]]

diff: https://ci.embassy.dev/jobs/81dafa02d706/artifacts/diff.html

[embassy-ci[bot]]

diff: https://ci.embassy.dev/jobs/7f504b5f0c3a/artifacts/diff.html