STM32G0: Fix USBSEL Variants for selecting HSE and PLL1_Q as USB Clock

[ijager]

This is a fix for https://github.com/embassy-rs/embassy/issues/3223

This swaps the values of HSE and PLL1_Q variants so that they are correct.

Note that the register definition 5.4.22 in reference manual RM0444 is wrong but that this fix matches the c header files provided by ST for STM32Cube.

// stm32g0xx_hal_rcc_ex.h#L437 

#if defined(RCC_CCIPR2_USBSEL)
/** @defgroup RCCEx_USB_Clock_Source USB Clock Source
   * @{
   */
#if defined(RCC_HSI48_SUPPORT)
#define RCC_USBCLKSOURCE_HSI48         0x00000000U            /*!< HSI48 oscillator clock selected as USB clock */
#endif /* RCC_HSI48_SUPPORT */
#define RCC_USBCLKSOURCE_HSE           RCC_CCIPR2_USBSEL_0  /*!< HSE oscillator clock selected as USB clock */
#define RCC_USBCLKSOURCE_PLL           RCC_CCIPR2_USBSEL_1  /*!< PLL "Q" selected as USB clock */
/**
   * @}
   */
#endif /* RCC_CCIPR2_USBSEL */

For PLL we need to set bit RCC_CCIPR2_USBSEL_1. And RCC_CCIPR2_USBSEL_1 = 0x2:

// stm32g0b1xx.h#L6910

#define RCC_CCIPR2_USBSEL_Pos             (12U)
#define RCC_CCIPR2_USBSEL_Msk             (0x3UL << RCC_CCIPR2_USBSEL_Pos)     /*!< 0x00003000 */
#define RCC_CCIPR2_USBSEL                 RCC_CCIPR2_USBSEL_Msk
#define RCC_CCIPR2_USBSEL_0               (0x1UL << RCC_CCIPR2_USBSEL_Pos)      /*!< 0x00001000 */
#define RCC_CCIPR2_USBSEL_1               (0x2UL << RCC_CCIPR2_USBSEL_Pos)      /*!< 0x00002000 */

See also: https://klipper.discourse.group/t/stm32g0-usb-clock-config/4487/2

Tested on STM32G0B1RETx

[embassy-ci[bot]]

diff: https://ci.embassy.dev/jobs/6806965e351b/artifacts/diff.html