Use SystemVerilog instead of Verilog

[imphil]

The tutorial slides contain (rightfully so) SystemVerilog statements (like always_comb). For those statements to be available to yosys, the easiest way is to rename all .v files to .sv and adjust the Makefile accordingly to pick up those files. No other changes to the commands are necessary.

It's probably best to do this after the current tutorial session for the next one to reduce confusion.

[jeremybennett]

Many thanks - that's a good idea. I think there may be an option to yosys to say .v is SystemVerilog, in which case we can just change the Makefiles.