Add spike RISC-V simulator support

[widlarizer]

As unhelpful it may be for performance testing, spike is a valid target for evaluating compilers on code size while ensuring the benchmarks are still functional. This directory has been glued together from various fragments of community code with original licenses ensured to be GPL compatible and copyright notices modified with SPDX tags added. Some open questions:

• Is crt0 allowed to be present at all, with some added switch? The motivation is testing RISC-V LLVM
• Should the sources be merged to be consistent, which would possibly harm manual and automated licensing compatibility reviews?

[widlarizer]

Resulting time parsing isn't implemented yet due to https://github.com/riscv-software-src/riscv-isa-sim/issues/1493

[widlarizer]

That implemented cycle count parsing. The ISA is hard coded to RV32GC and letting that be configurable is another open question