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eminfedar / fedar-f1-rv64im

5-Stage Pipelined RV64IM RISC-V CPU design in Verilog.
MIT License
185 stars 17 forks source link

Hardware Design Schematic of connections and blocks #3

Open Ritwik-Kaushik opened 10 months ago

Ritwik-Kaushik commented 10 months ago

Can you pls share your hardware design schematic of connections and blocks. And along with the gtk save file to view all the signals in the logical manner.

eminfedar commented 10 months ago

Generated VCD files are there: https://github.com/eminfedar/fedar-f1-rv64im/tree/main/testbench/vcd, The enums to map numbers to names in GTKWave are here: https://github.com/eminfedar/fedar-f1-rv64im/tree/main/gtkwave

You can directly open vcd files in GTKWave with gtkwave file.vcd

There 's no schematic and connection blocks. Pure verilog.

Ritwik-Kaushik commented 10 months ago

Thanks for reply. Requesting the flow diagram as I am modifying your design for the Forwarding logic, and it would be easier to implement if the I/p and o/p signals and visually known. Any way thanks. One final request pls tell me the signals which you had included below this image (Not visible in the image , GTK had to be scroll down for those). gtkwave-image