Whilst implementing the Windows support for FRAM I had to investigate this chip and learn everything about it. I took me a while to work out if I had the correct data sheets based on the documentation, luckily the C++ examples have two copies one additional for Navio+. So I worked out what was going on, that FRAM was upgraded from 4K to 32K in Navio+.
In your documentation you only refer to the old 4K Navio MB85RC04V. When you have time maybe you should correct that. It should explain there are two different chips and hence two different samples, that Navio has 32K available and link to the new new data sheet:
https://www.fujitsu.com/us/Images/MB85RC256V-DS501-00017-3v0-E.pdf
Also the complexity of splitting the 9th address bit into the I2C slave address is removed on the newer chip (with two whole address bytes instead). So it really needs to revised wording.
Whilst implementing the Windows support for FRAM I had to investigate this chip and learn everything about it. I took me a while to work out if I had the correct data sheets based on the documentation, luckily the C++ examples have two copies one additional for Navio+. So I worked out what was going on, that FRAM was upgraded from 4K to 32K in Navio+.
In your documentation you only refer to the old 4K Navio MB85RC04V. When you have time maybe you should correct that. It should explain there are two different chips and hence two different samples, that Navio has 32K available and link to the new new data sheet: https://www.fujitsu.com/us/Images/MB85RC256V-DS501-00017-3v0-E.pdf
Also the complexity of splitting the 9th address bit into the I2C slave address is removed on the newer chip (with two whole address bytes instead). So it really needs to revised wording.