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emsec / hal

HAL – The Hardware Analyzer
MIT License
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VHDL parser should be able to parse a netlist that is not flattened #156

Closed not-a-trojan closed 5 years ago

not-a-trojan commented 5 years ago

Is your feature request related to a problem? Please describe. With the availability of modules, the vhdl parser should be able to parse a netlist with hierarchy.

The solution we will implement All entities are parsed separately before inserted into the top entity as modules. Signal names on inputs/outputs can be taken from the parent entity, internal signals are prefixed with the entity name.

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swallat commented 5 years ago

I strongly support this feature.

not-a-trojan commented 5 years ago

Update: The feature is basically done in its respective feature branch. It now needs testing.

swallat commented 5 years ago

@devhoffmann: Any suggestions how we should proceed?

not-a-trojan commented 5 years ago

Now merged into the master and used as a default. The old parser is still available using the '--language vhdl_old' switch