Bugfix verilog parser: avoid access to deleted nets

[joern274]

Bugfix: in the last block of method VerilogParser::construct_netlist modules are tested whether a ground- or voltage supply pin needs to be created.

However, appropriate nets m_one_net or m_zero_net might have been deleted at an earlier stage, thus resulting in memory access error when testing.

These tests are omitted in this fix.