When using other tools to synthesize the HDL, they error out because assign happens to a wire which is not defined yet (that is, the wire is declared after there is an assign using it).
Rearranging the lines, so that the ordering becomes input/output/inout, then wire, then assign, and then module instantiations, then the file successfully snythesizes.
When using other tools to synthesize the HDL, they error out because
assignhappens to a wire which is not defined yet (that is, thewireis declared after there is anassignusing it).Rearranging the lines, so that the ordering becomes
input/output/inout, thenwire, thenassign, and then module instantiations, then the file successfully snythesizes.