emu-russia / dmgcpu

DMG CPU Reverse Engineering
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Verify CLK trees #226

Closed ogamespec closed 6 months ago

ogamespec commented 6 months ago

We need to verify that CLK trees are correctly represented and their polarity is treated correctly in all project materials.

ogamespec commented 6 months ago

Overall looks like no problems, except for this one:

// Regular posedge DFF (dual rails)
module seq_dff_posedge_comp ( d, clk, cclk, q );

    input d;    
    input clk;
    input cclk;
    output q;

    reg val;
    initial val = 1'bx;

    // XXX: Initially, clk and cclk were mixed up when parsing the netlist. So read here cclk as clk. Not a very nice mix-up, but this is always the case with clk.
    always @(posedge cclk) begin
        val <= d;
    end

    assign q = val;

endmodule // seq_dff_posedge_comp