Closed Rodrigodd closed 6 months ago
Thank you, I'll have another good look at Regs Block. It's really messed up with the complements there, so I missed that feature.
Oh, I meant to open this PR as Draft. At least, I didn't want to merge the last commit, because investigation.md
is just notes I take as I investigate things, and debuging_instructions.gtkw
is not very portable. It contains an absolute path to the .vcd
file, so it brakes when copying it to another machine. You need to manually patch it to make it work.
But if you are good with merging it, no problem.
It contains an absolute path to the .vcd file, so it brakes when copying it to another machine.
I think it's fine, everything loads properly on Windows. I just loaded the .vcd file by hand beforehand. Very handy, thanks for this method. I was wondering how to save signals without adding them manually every time :D
investigation.md
This is also fine, I like it :)
This PR contains my test setup for investigating problems in the execution of instruction in the CPU. My goal is to execute actual ROMs in the
dmg-sim
repo, but it is much faster to run simulations here.For now ,it just adds some debug signals for PC and SP, and a read-only memory for
Bogus_HW
, but I expect to add read/write memory, and many more debug signals (at least for program visible state, like registers and interrupt signals) as things progress.Currently, it is blocked by two major problems that I found, which I will create issues for.
This is the result of the simulation, with the issue about inverted registers fixed: