Rodrigodd commented 6 months ago

From #238. To fix it there, I removed the not operator from the assignment to Z_in and W_in, but I don't know how to confirm if this should be the actual fix, there are many other possible positions where the signal could be inverted or not (the registers could for example store the value of the registers inverted and then straight them when loading).

Below is my investigation of the flow of data from the databus to the registers, extracted from investigating.md in the linked PR, with added screenshots.

HL is inverted in the address bus

H and L are stored in ReqH/r3q and ReqL/r2q, respectively, inverted. H can go to abus, bbus or dbus, and L can go to abus, bbus or cbus. They go to the bus through an inverter, so they have they original value.

In this instruction, H goes to dbus and L goes to cbus. dbus cbus go through an BusKeeper, and them inverted again into the AdressBus (or A).

From the comments in IDU.v, the code expects that the internal register actually holds the straight value of the ISA registers, but they are inverted in the current form. This was also seen in the JP instruction, and I fix that there by inverting the Zbus, but maybe we need to invert something more fundamental, like the value read from the memory?

H: r3q -> dbus -> BusKeeper -> AddressBus (inverted)
L: r2q -> cbus -> BusKeeper -> AddressBus (inverted)

Path from databus to register A

D -> DataLatch -> DL -> Z_in (inverted) -> zbus -> bbus (straighted) -> bbq -> DV (inverted) -> Res -> fbus -> RegA

So RegA/r1q contains the inverted value of A.

In screenshot, the execution of the instruction LD A, $BC (3e bc).

Path from databus to register HL

H: D -> DataLatch -> DL -> W_in (inverted) -> wbus -> fbus -> RegH
L: D -> DataLatch -> DL -> Z_in (inverted) -> zbus -> ebus -> RegL

So HL are also stored inverted in the registers.

In screenshot, the execution of the instruction LD HL, $DE80 (21 80 de).

Path from databus to register SP

SP high: D -> DataLatch -> DL -> W_in (inverted) -> wbus -> sph_nd (inverted) -> SPH (inverted)
SP low: D -> DataLatch -> DL -> Z_in (inverted) -> zbus -> spl_nd (inverted) -> SPL (inverted)

So SP is also stored inverted in the registers.

In screenshot, the execution of the instruction LD SP, $AACC (31 cc aa).

Path from databus to PC

PC high: D -> DataLatch -> DL -> W_in (inverted) -> wbus -> pch_nd (inverted) -> PCH (inverted)
PC low: D -> DataLatch -> DL -> Z_in (inverted) -> zbus -> pcl_nd (inverted) -> PCL (inverted)

So PC is also stored inverted in the registers.