Try to fix verilator and tidy up `cpu_instrs` emulation

[Rodrigodd]

This PR contains the following changes:

• Tried to make Verilator simulation work: in the end, the simulation didn't work. I think Verilator doesn't have enough support for high-impedance signals to simulate this project.
• Replaced .bat files with a Makefile: the .bat file never worked for me, due to the order of the files in the glob expansion, so I replaced them with a Makefile. Not sure if you like this change.
• Allowed passing a ROM path to the simulation as a preprocessor define (and through Makefile variable).
• Implemented a boot sequence for Bogus_HW.
• Implemented serial output.
• Removed all #0 delays: not sure if they were actually needed, let me know if they were.
• Replaced many inouts with input or output: also not sure if it was needed.

These changes were made to allow debugging cpu_instrs more easily, or in an attempt to make Verilator work. If you are not happy with any of the changes, please let me know.

I managed to run cpu_instrs once, which resulted in an error code 07 in the first test, and then printed the start message again, but I didn't investigate further. The vvp is running the simulation at the speed of around 8 real hours per simulated second. This isn't great, considering that the full test takes 60s to run; this would take 20 days to run.

So I tried to make Verilator work, but without success (its emulation was running at 12min per emulated second, although completely wrong).

dmg-sim, without this CPU, takes "only" 1h15min per simulated second, if I remember correctly. Maybe there is a way to speed up the simulation.

[ogamespec]

Replaced many inouts with input or output: also not sure if it was needed.

The idea was to make it obvious from any module that inout is a bus. But if some modules drive it and some use it (input), I think it's no big deal. Whoever needs it will figure it out :)

As for everything else, it's fine. Thanks :)

As for the slow simulation - I am also very sad about it and was sad for a few days :) I think we need to choose another strategy for core verification, specifically to test each opcode individually with a small program. Maybe even cut blargg tests for this purpose. Waiting for days for results is not fun at all :)

[ogamespec]

I'll hold a little PR for aftershocks, I'll run it a little later today if nothing comes on top. Thank you!