DCI_CASCADE property in .tcl file contradicts schematic

[hansfbaier]

Hello, I found a contradiction between the .tcl settings and schematic. In the .tcl file, we read:

set_property DCI_CASCADE {32} [get_iobanks 34]

But in the schematic, the DDR3_VRP/DDR3_VRN reference resistors are connected to the reference inputs of Bank 34, while the reference inputs of bank 32 and 33 are conected to the onboard LEDs:

Which means that, according to the schematic and UG471, the configuration should be as follows:

set_property DCI_CASCADE {34} [get_iobanks 32 33]

Because 34 is the master bank with the reference resistors connected and 32 and 33 are the slave banks. (see also https://support.xilinx.com/s/article/47499?language=en_US)

[dduerner]

Hi Hans

I think you are correct for UCF syntax, but for XDC syntax it is seems to be correct in the reference design, as written in the UG912 on page 192/193:

set_property DCI_CASCADE {slave_banks} [get_iobanks master_bank]

In UG471 on page 46/47 the UCF syntax is mentioned.

Further Xilinx Article 38913 shows the difference between the XDC & UCF syntax.

[hansfbaier]

Yes that's the way it really seems to work. Thanks!