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Weird commenting in wiring.c for FR24343 #1034

Closed V1DEOJAMES closed 5 years ago

V1DEOJAMES commented 5 years ago

I have noticed some inconsistency when looking into using VLO for ACLK .

The comments suggest that ALCK is sourced via VLO but the code actually uses SELAREFOCLK. SELAVLOCLK is missing from msp430fr2433.h so simply replacing it does not help.

If someone could clear up if the comments are wrong or if there should be a definition for ACLK to source from VLO (Which is definitely my preference 😋 ).

Thanks!

#if (defined(__MSP430FR2XX_4XX_FAMILY__) && (defined(__MSP430_HAS_CS__) || defined(__MSP430_HAS_CS_A__)))
    /* section for FR2xx and FR4xx devices */
 #if (defined(INIT_LFXTAL_PINS))
    INIT_LFXTAL_PINS;
 #else
   #if (defined(__MSP430_HAS_PORTJ_R__))
    /* All pins as output to reduce power consumption */
    PJDIR = 0xFF;
    /* Set all pins low to reduce power consumption */
    PJOUT = 0;
    /* Enable PJ.4/5 as XTAL pins */
    PJSEL0 = BIT4 | BIT5;
   #endif   
 #endif 

    /* LFXT can take up to 1000ms to start.
     * Go to the loop below 4 times for a total of 2 sec timout.
     * If a timeout happens due to no XTAL present or a faulty XTAL
     * set ACLK source as VLO (~8kHz) */
    uint16_t timeout = 0x4;
    do {
        timeout--;
        /* Clear Oscillator fault flags */
        CSCTL7 &= ~(DCOFFG|XT1OFFG|FLLULIFG);
        /* Clear the Oscillator fault interrupt flag */
        SFRIFG1 &= ~OFIFG;
        /* @ 1MHz startup: delay for 500ms */
        __delay_cycles(500000L * (F_CPU/1000000L));
        if(!timeout) break;
    /* Test the fault flag */
    }while (SFRIFG1 & OFIFG);

    /* If starting the XTAL timed out then fall back to VLO */
    if(!timeout) {
        /* ACLK = VLO = ~ 12 KHz */
        vlo_freq = 8000;
        /* Source ACLK from REFO */
        CSCTL4 |=  SELA__REFOCLK;
    }
#endif
StefanSch commented 5 years ago

Hi,

thanks for reporting this issues - it just had been solved last week, see: https://github.com/energia/msp430-lg-core/pull/78