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Stellaris LM4F: MISO doesn't work on SPI ports 0 and 3 #255

Closed rei-vilo closed 11 years ago

rei-vilo commented 11 years ago

Summary:

GPIO 9.1 Some GPIO register bits default to the incorrect state Description: The AFSEL bits for the following pins are set at reset, resulting in the pins defaulting to their alternate function: This error in pin functionality may create pin conflict during any type of reset with the following signals: Signal PA4 Function SSI0Rx I/O Input Level Tristate

and proposes as workaround

Workaround: To reconfigure the pins to their intended reset state (GPIO Input, GPIODEN =0), software must clear the corresponding bits in the GPIOAFSEL and GPIODEN registers for the associated pins. For pins PD7 and PF0, software must clear the corresponding AFSEL bits using the register commit control procedures described in the Commit Control section in the General-Purpose Input/Outputs chapter in the data sheet. Note that PD7 and PF0 should be grounded, if possible, to prevent triggering an NMI. If that is not possible, an NMI handler must be implemented in case a High level is applied to PD7 or PF0 before they can be reconfigured. For PD7, the PMC7 assignment of 0x3 is not valid, so it does not cause any issues. However, for PF0, the PMC0 assignment of 0x3 specifies CAN0Rx. If the system design requires CAN0Rx to be on another pin, the PMC0 field for Port F must be assigned to another function or cleared. Silicon Revision Affected: A1 Fixed: Fixed on A3.

rei-vilo commented 11 years ago

I've tried on my two Srptellars boards. I suspect some kind of initialisation.

rei-vilo commented 11 years ago

Now, the MCUs on my two Stellaris LaunchPads aren't labelled LM4F120H5QR but LX4F120H5QR.

lx4f120h5qr

As I was an early adopter, were the MCUs from a pre-production batch?

rei-vilo commented 11 years ago

See issue #256 Fix for issue #255.