Add/Verify OpenOCD VexrRiscv-SMP JTAG Debug.

enjoy-digital / LimeSDR-XTRX_LiteX_GW

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Closed enjoy-digital closed 4 weeks ago

enjoy-digital commented 1 month ago

[x] Swtch CPU to VexRiscv-SMP.
[x] Add/verify support to the target.
[x] Add local instruction to do JTAG Debugging (from https://github.com/enjoy-digital/litex/wiki/JTAG-GDB-Debugging-with-VexRiscv-SMP-NaxRiscv-VexiiRiscv-CPUs).

enjoy-digital commented 1 month ago

Should be done on litex_xtrx.py target with BSCAN.

enjoy-digital commented 1 month ago

@trabucayre: Can you update, is "Add/verify support to the target." done?

trabucayre commented 1 month ago

Done: with --bscan-option vexriscv-smp is configured with privileged-debug, hardware-breakpoint=4 and a BSCAN primitive is added/connected

enjoy-digital commented 4 weeks ago

Done.