Open jedrzejboczar opened 4 years ago
In _LiteDRAMBISTGenerator the base address is being aligned to dram_port.data_width and length denotes the number of commands issued (https://github.com/enjoy-digital/litedram/blob/master/litedram/frontend/bist.py#L187).
_LiteDRAMBISTGenerator
base
dram_port.data_width
length
In _LiteDRAMPatternGenerator the address passed in init is not being shifted. We should probably treat it the same as in _LiteDRAMBISTGenerator by changing https://github.com/enjoy-digital/litedram/blob/60b618eebaebabeea07f9d1082653d1888fb89f4/litedram/frontend/bist.py#L280 to dma_sink_addr.eq(addr_port.dat_r[ashift:]).
_LiteDRAMPatternGenerator
init
dma_sink_addr.eq(addr_port.dat_r[ashift:])
Changing this will also require updating benchmarks to generate proper access patterns depending on dram_port data width. I'll work on this after adding some more BIST unit tests.
dram_port
In
_LiteDRAMBISTGeneratorthebaseaddress is being aligned todram_port.data_widthandlengthdenotes the number of commands issued (https://github.com/enjoy-digital/litedram/blob/master/litedram/frontend/bist.py#L187).In
_LiteDRAMPatternGeneratorthe address passed ininitis not being shifted. We should probably treat it the same as in_LiteDRAMBISTGeneratorby changing https://github.com/enjoy-digital/litedram/blob/60b618eebaebabeea07f9d1082653d1888fb89f4/litedram/frontend/bist.py#L280 todma_sink_addr.eq(addr_port.dat_r[ashift:]).Changing this will also require updating benchmarks to generate proper access patterns depending on
dram_portdata width. I'll work on this after adding some more BIST unit tests.