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enjoy-digital / litedram

Small footprint and configurable DRAM core
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use ODDRX1F for command and address output on ECP5 #198

Closed kingoflolz closed 4 years ago

kingoflolz commented 4 years ago

From #194

Confirmed that versa_ecp5 compiles, but not tested on real hardware

daveshah1 commented 4 years ago

The latency between the two primitive may well be different, so a test on hardware would definitely be good.

enjoy-digital commented 4 years ago

@kingoflolz: thanks for #198, i did a test with it on a Trellisboard but it's not working unfortunately. This would need to be investigated further in simulation or/and on hardware.

kingoflolz commented 4 years ago

Could the issue be with using the sys2x reset with the sys clock domain on the ODDRX1F? I do not have the equipment necessary to really dig into this (on hardware) unfortunately.

daveshah1 commented 4 years ago

I think the bigger problem is likely the unknown phase shift between sys2x (which is creating the output clock for the DDR) and sys (which is now clocking the command/address outputs). It might be possible to calibrate out this delay with an output DELAYF on the command/address signals but this feels like something that should only be enabled if really needed and ODDRX2F used for all platforms with non-broken PCB layouts.

enjoy-digital commented 4 years ago

@kingoflolz: do you have a specific use case in mind for this? Because since this does not seem to be as simple as expected, like @daveshah1, i think this is something we should only be supporting if really required and if a working solution is provided.

kingoflolz commented 4 years ago

I'm doing bringup on a custom ECP5 board which has some command and address pins routed to the top IO bank. As it lookes like its going to be quite complicated, I might just give up dram for this revision and route everything to the left and right IO bank for the next revision.

kingoflolz commented 4 years ago

I do find it interesting that the lattice datasheet does suggest the top IO bank can be used for DDR command and addr, I wonder if the lattice DDR3 IP handles that case. image

enjoy-digital commented 4 years ago

@kingoflolz: thanks for the info. That's indeed probably possible, but requires some investigation to understand what is miss-behaving. I'll try to see if i can spend 1-2 hours on this but not sure i'll be able to investigate more.

enjoy-digital commented 4 years ago

@kingoflolz: sorry i won't be able to spend time investigating this and i'm not sure it will be the case for someone else in the near future. I'll however be happy to test and integrate a validated solution if provided.