Closed jedrzejboczar closed 3 years ago
I fixed the main problems in the implementation and tested it on minispartan6 board with frequency 80MHz:160MHz getting correct results (./minispartan6.py --build --load --csr-csv csr.csv --uart-name crossover --cpu-variant lite --integrated-sram-size 4096 --sdram-sys2x
+ uartbone + Platform(device="xc6slx9")
+ https://github.com/litex-hub/litex-boards/pull/91):
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Build your hardware, easily!
(c) Copyright 2012-2020 Enjoy-Digital
(c) Copyright 2007-2015 M-Labs
BIOS built on Jul 14 2020 11:35:23
BIOS CRC passed (f290e714)
Migen git sha1: b1b2b29
LiteX git sha1: 6671eb62
--=============== SoC ==================--
CPU: VexRiscv @ 80MHz
BUS: WISHBONE 32-bit @ 4GiB
CSR: 8-bit data
ROM: 32KiB
SRAM: 4KiB
L2: 8KiB
MAIN-RAM: 32768KiB
--========== Initialization ============--
Initializing DRAM @0x40000000...
SDRAM now under software control
SDRAM now under hardware control
Memtest at 0x40000000...
[########################################]
[########################################]
Memtest OK
Memspeed at 0x40000000...
Writes: 146 Mbps
Reads: 169 Mbps
--============== Boot ==================--
Booting from serial...
Press Q or ESC to abort boot completely.
sL5DdSMmkekro
Timeout
No boot medium found
--============= Console ================--
litex> ident
Ident: LiteX SoC on MiniSpartan6 2020-07-14 11:35:22
litex>
Thanks! Merged.
@jedrzejboczar: just for info, i've been able to reproduce your results and also boot Linux with it on the Minispartan6 (with a boot speed up), thanks.
Corresponding issue: https://github.com/enjoy-digital/litedram/issues/183
This adds a wrapper over GENSDRPHY and option to use it on ULX3S (with https://github.com/enjoy-digital/litex/pull/563 PR).
But this does not yet work correctly, I've been trying to find an error, but with no success. @enjoy-digital could you please take a look if I'm missing something?