Add dynamic write latency calibration.

[daveshah1]

Would it be useful for you if I tested this on the Alveo U250 tomorrow?

[enjoy-digital]

@daveshah1: thanks, i'm planning to do some tests tomorrow on the BCU1525 with this (i implemented it to handle corner cases on a XCVU440/DDR4 setup). If it's not taking too long for you to test on the Alveo U250, that would be useful to have your feedback yes.

[daveshah1]

These are my test results. Data scan passes for the last 32 bits; write latency and read levelling passes for the first 32 bits:

        __   _ __      _  __
       / /  (_) /____ | |/_/
      / /__/ / __/ -_)>  <
     /____/_/\__/\__/_/|_|
   Build your hardware, easily!

 (c) Copyright 2012-2020 Enjoy-Digital
 (c) Copyright 2007-2015 M-Labs

 BIOS built on Oct 13 2020 10:10:08
 BIOS CRC passed (dad28515)

 Migen git sha1: --------
 LiteX git sha1: 4d553a6f

--=============== SoC ==================--
CPU:     VexRiscv @ 125MHz
BUS:     WISHBONE 32-bit @ 4GiB
CSR:     32-bit data
ROM:     32KiB
SRAM:        8KiB
L2:      8KiB
SDRAM:       1048576KiB 64-bit @ 1000MT/s (CL-9 CWL-9)

--========== Initialization ============--
Initializing SDRAM @0x40000000...
Switching SDRAM to software control.
Write leveling:
  Cmd/Clk scan:
  |00000000  |0000  |0000  |0000| best: -1
  Setting Cmd/Clk delay to -1 taps.
  Data scan:
  m0: |1111111111111000000000| delay: -
  m1: |1111111111110000000000| delay: -
  m2: |1111111110000000000000| delay: -
  m3: |1111100000000000000000| delay: -
  m4: |0000000000011111111111| delay: 165
  m5: |0000000000000000001111| delay: 274
  m6: |1000000000000000000011| delay: 307
  m7: |0000000000000000000111| delay: 300
Write latency calibration:
m0:6 m1:6 m2:6 m3:6 m4:0 m5:0 m6:0 m7:0 
Read leveling:
  m0, b0: |00000000000000000000000000000000| delays: -
  m0, b1: |00000000000000000000000000000000| delays: -
  m0, b2: |00000000000000000000000000000000| delays: -
  m0, b3: |11111111110000000000000000000000| delays: 73+-73
  m0, b4: |00000000000011111111111111110000| delays: 305+-132
  m0, b5: |00000000000000000000000000000011| delays: 491+-20
  m0, b6: |00000000000000000000000000000000| delays: -
  m0, b7: |00000000000000000000000000000000| delays: -
  best: m0, b04 delays: 308+-129
  m1, b0: |00000000000000000000000000000000| delays: -
  m1, b1: |00000000000000000000000000000000| delays: -
  m1, b2: |00000000000000000000000000000000| delays: -
  m1, b3: |11111111111111000000000000000000| delays: 110+-110
  m1, b4: |00000000000000001111111111111111| delays: 382+-125
  m1, b5: |00000000000000000000000000000000| delays: -
  m1, b6: |00000000000000000000000000000000| delays: -
  m1, b7: |00000000000000000000000000000000| delays: -
  best: m1, b04 delays: 381+-126
  m2, b0: |00000000000000000000000000000000| delays: -
  m2, b1: |00000000000000000000000000000000| delays: -
  m2, b2: |00000000000000000000000000000000| delays: -
  m2, b3: |01111111111111111000000000000000| delays: 136+-129
  m2, b4: |00000000000000000000111111111111| delays: 408+-104
  m2, b5: |00000000000000000000000000000000| delays: -
  m2, b6: |00000000000000000000000000000000| delays: -
  m2, b7: |00000000000000000000000000000000| delays: -
  best: m2, b03 delays: 141+-130
  m3, b0: |00000000000000000000000000000000| delays: -
  m3, b1: |00000000000000000000000000000000| delays: -
  m3, b2: |10000000000000000000000000000000| delays: 08+-08
  m3, b3: |00001111111111111110000000000000| delays: 172+-126
  m3, b4: |00000000000000000000011111111111| delays: 425+-87
  m3, b5: |00000000000000000000000000000000| delays: -
  m3, b6: |00000000000000000000000000000000| delays: -
  m3, b7: |00000000000000000000000000000000| delays: -
  best: m3, b03 delays: 173+-123
  m4, b0: |00000000000000000000000000000000| delays: -
  m4, b1: |00000000000000000000000000000000| delays: -
  m4, b2: |00000000000000000000000000000000| delays: -
  m4, b3: |00000000000000000000000000000000| delays: -
  m4, b4: |00000000000000000000000000000000| delays: -
  m4, b5: |00000000000000000000000000000000| delays: -
  m4, b6: |00000000000000000000000000000000| delays: -
  m4, b7: |00000000000000000000000000000000| delays: -
  best: m4, b00 delays: -
  m5, b0: |00000000000000000000000000000000| delays: -
  m5, b1: |00000000000000000000000000000000| delays: -
  m5, b2: |00000000000000000000000000000000| delays: -
  m5, b3: |00000000000000000000000000000000| delays: -
  m5, b4: |00000000000000000000000000000000| delays: -
  m5, b5: |00000000000000000000000000000000| delays: -
  m5, b6: |00000000000000000000000000000000| delays: -
  m5, b7: |00000000000000000000000000000000| delays: -
  best: m5, b00 delays: -
  m6, b0: |00000000000000000000000000000000| delays: -
  m6, b1: |00000000000000000000000000000000| delays: -
  m6, b2: |00000000000000000000000000000000| delays: -
  m6, b3: |00000000000000000000000000000000| delays: -
  m6, b4: |00000000000000000000000000000000| delays: -
  m6, b5: |00000000000000000000000000000000| delays: -
  m6, b6: |00000000000000000000000000000000| delays: -
  m6, b7: |00000000000000000000000000000000| delays: -
  best: m6, b00 delays: -
  m7, b0: |00000000000000000000000000000000| delays: -
  m7, b1: |00000000000000000000000000000000| delays: -
  m7, b2: |00000000000000000000000000000000| delays: -
  m7, b3: |00000000000000000000000000000000| delays: -
  m7, b4: |00000000000000000000000000000000| delays: -
  m7, b5: |00000000000000000000000000000000| delays: -
  m7, b6: |00000000000000000000000000000000| delays: -
  m7, b7: |00000000000000000000000000000000| delays: -
  best: m7, b00 delays: -
Switching SDRAM to hardware control.
Memtest at 0x40000000 (2MiB)...
  Write: 0x40000000-0x40200000 2MiB     
   Read: 0x40000000-0x40200000 2MiB     
  bus errors:  128/256
  addr errors: 4096/8192
  data errors: 262144/524288
Memtest KO
Memory initialization failed

--============= Console ================--

litex>

As this is RDIMM based, it might be that the RCD config still needs further tuning though.