search

enjoy-digital / litedram

Small footprint and configurable DRAM core
Other
375 stars 120 forks source link

init: make the write leveling MR bit configurable #232

Closed jedrzejboczar closed 3 years ago

jedrzejboczar commented 3 years ago

This is a part of splitting https://github.com/enjoy-digital/litedram/pull/224 into smaller PRs. Requires corresponding PR in litex: https://github.com/enjoy-digital/litex/pull/791.

In LPDDR4 the write leveling mode is configured with MR2[7] instead of MR1[7]. This PR changes the way get_sdram_phy_init_sequence returns mode register values. Now it should return a dictionary {mr_num: mr_value, ...}. Instead of generating DDRX_MR1 define we now have 3 DDRX_MR_WRLVL_* defines that specify the mode register changes required to enter/leave write leveling mode.

Note that DDRX_MR_WRLVL_BIT is the bit that gets flipped (with xor), so DDRX_MR_WRLVL_RESET is the state when write leveling is disabled and software just filps given bit when entering write leveling mode and writes the original DDRX_MR_WRLVL_RESET value when leaving.

jedrzejboczar commented 3 years ago

test_genesys2 fails because the litex used in CI doesn't include https://github.com/enjoy-digital/litex/pull/791