[ ] Latency optimization
DoubleRateLPDDR4PHY currently introduces some latency in the intermediate (de-)serialization stage that we could decrease.
[ ] Dynamic tCCD
In LPDDR4 tCCD is different for the WRITE/MASKED-WRITE commands (e.g. 8 vs 32 ck), currently LPDDR4 PHY optionally supports switching between these commands, but there is no way to modify tCCD dynamically so there is no point in ever using WRITE over MASKED-WRITE
[ ] LPDDR4-compatible Refresher
In LPDDR4 we need 2 separate commands to perform ZQCS (start and latch) and between them other commands can be issued. Currently Refresher issues a single command. We cannot handle this in PHY because there is no way to halt other commands while performing the latch command.
[ ] tRAS max
I noticed there seems to be a limitation on maximum row active time. If I understand it correctly, we are required to close a row after that amount of time (e.g. tRAS_max = min(9*tREFI*refresh rate, 70.2 us)). As for now it didn't seem to cause problems but we most likely should add it. It would have to be enforced by the controller.
[ ] Target Row Refresh
LPDDR4 modules can support optional TRR feature to prevent row hammer attack, but this needs to be supported in the memory controller.
[ ] Data Bus Inversion
It is possible to enable DBI feature. Currently we use DMI lines only for data mask.
[ ] Vref training
LPDDR4 describes Vref training procedure for CA and DQ buses. It could be used to improve performance at high frequencies. This would, among others, require additional BIOS software.
[x] Write training
There is additional training step that is used to match the delays between DQ an DQS lines, which could help to improve performance at high frequencies.
[ ] Frequency set points
LPDDR4 includes two sets of parameters in mode registers for two different operating frequencies. It is possible to start operation at lower (safe) frequency and then perform training at the higher frequency by switching between the frequency set points. This would be useful for high frequencies when we encounter issues when trying to send commands (so cannot do the training).
As noted in https://github.com/enjoy-digital/litedram/pull/224 there are some features needed to LPDDR4 support. I listed all the things that came to my mind, though some may not be needed.
tRAS_max = min(9*tREFI*refresh rate, 70.2 us)). As for now it didn't seem to cause problems but we most likely should add it. It would have to be enforced by the controller.Some of the points are more precisely described in https://github.com/enjoy-digital/litedram/pull/224#issuecomment-808090924.