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enjoy-digital / litedram

Small footprint and configurable DRAM core
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Generation with AXI interface #254

Closed lindajames101 closed 3 years ago

lindajames101 commented 3 years ago

Is there any documentation or procedure for generation with axi signals?

enjoy-digital commented 3 years ago

Hi @lindajames101,

to add AXI User ports, you can look at the LiteDRAM generator: https://github.com/enjoy-digital/litedram/blob/master/litedram/gen.py#L596-L647 or try to generate the cores as a standalone with cd examples && litedram_gen arty.yml that exposes an AXI User port: https://github.com/enjoy-digital/litedram/blob/master/examples/arty.yml#L35-L38.