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enjoy-digital / litedram

Small footprint and configurable DRAM core
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LPDDR5 support #270

Closed jedrzejboczar closed 2 years ago

jedrzejboczar commented 3 years ago

The changes include and require https://github.com/enjoy-digital/litedram/pull/269. To see only LPDDR5 changes use: https://github.com/antmicro/litedram/compare/jboc/dfi-converter-new...jboc/lpddr5-rebase

This PR adds an initial implementation of LPDDR5 PHY. I am creating this as a draft for now, as there are some limitations in the PHY implementation, and some additional work needs to be done. Nevertheless it might be good to already have such a draft here now. A short summary of the required PRs:

The PHY has been tested in simulation only, due to lack of hardware to test on. The most important LPDDR5 logic is already there and it should be ready for testing on hardware. We will also be doing additional tests in simulation.

The implementation is based on the same structure as LPDDR4 PHY (LPDDR4 readme) :

litedram/phy/lpddr5
├── basephy.py     # general LPDDR5 PHY logic
├── commands.py    # translation of DFI commands into CS/CA sequences
├── __init__.py
├── simphy.py      # PHY for use in simulation
├── sim.py         # DRAM simulator
└── simsoc.py      # SoC for Verilator-based simulation

Tests have been added under tests/test_lpddr5.py and tests/test_sim_utils.py

acomodi commented 3 years ago

@enjoy-digital This PR is ready for review, can you please take a look?

I have fixed a simulation issue for which data bursts were not correctly issued. CI would need to be approved and manually run.

enjoy-digital commented 2 years ago

Thanks a lot @jedrzejboczar, @acomodi, this looks very good and clean. Let's merge and then update it in the future if required.