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enjoy-digital / litedram

Small footprint and configurable DRAM core
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The MAX sys_clk_freq supported of DDR4 #272

Closed uxilinx closed 2 years ago

uxilinx commented 2 years ago

Set sys_clk_freq=300 M in the .yml file. When gen.py is executed to generate bit file, the OSRDESE3 min period slack violation occurs in sys4x_pll_clk and the max skew violation occurs in sys_clk. Therefore, is sys_clk_freq set to 300 M not supported?

enjoy-digital commented 2 years ago

Hi @uxilinx,

the sys_clk_freq is limited by the max frequency of the clock buffer: 725/4=181MHz on a -2 Ultrascale, 850/4=212.5MHz on a -3 Ultrascale. It will probably work at higher speeds.