Closed jacquuelinee-b closed 2 years ago
Sorry I'm not sure to understand correctly the question, I'll try to answer but please have a look at https://github.com/enjoy-digital/litex/wiki/Feedback-Contribution-Support#feedback--contribution--support if I'm not understanding correctly the question to know which information is useful.
The initialization software is generated as part of the build also also compiled. If you want to avoid re-generating the core to update this software, you have to put this software in a writable memory and update it externally. It's for example possible to put the ROM is "rw" with integrated_rom_mode
parameter and then update it over one of the supported bridge of LiteX: https://github.com/enjoy-digital/litex/wiki/Use-Host-Bridge-to-control-debug-a-SoC or LiteX-Term: https://github.com/enjoy-digital/litex/wiki/Load-Application-Code-To-CPU. In this case, you'll only have to re-compile the software, not the FPGA design.
I am attempting to configure the LiteDram to boot from RAM using DDR3, is there a way to create the software initialization file for this without regenerating the core?