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enjoy-digital / litedram

Small footprint and configurable DRAM core
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Unable to run Litedram on Digilent Genesys2 #297

Closed fontamsoc closed 2 years ago

fontamsoc commented 2 years ago

https://gist.github.com/fontamsoc/97d446a381ae7341d3c0a586eadb382e

# examples/genesys2.yml
{
    # General ------------------------------------------------------------------
    "speedgrade": -2,      # FPGA speedgrade
    "cpu":        "None",  # CPU type (ex vexriscv, serv, None)
    "memtype":    "DDR3",  # DRAM type

    # PHY ----------------------------------------------------------------------
    "cmd_latency":     1,             # Command additional latency
    "sdram_module":    "MT41J256M16", # SDRAM modules of the board or SO-DIMM
    "sdram_module_nb": 4,             # Number of byte groups
    "sdram_rank_nb":   1,             # Number of ranks
    "sdram_phy":       K7DDRPHY,      # Type of FPGA PHY

    # Electrical ---------------------------------------------------------------
    "rtt_nom": "60ohm", # Nominal termination
    "rtt_wr":  "60ohm", # Write termination
    "ron":     "34ohm", # Output driver impedance

    # Frequency ----------------------------------------------------------------
    "input_clk_freq":   200e6, # Input clock frequency
    "sys_clk_freq":     100e6, # System clock frequency (DDR_clk = 4 x sys_clk)
    "iodelay_clk_freq": 200e6, # IODELAYs reference clock frequency

    # Core ---------------------------------------------------------------------
    "cmd_buffer_depth": 16,    # Depth of the command buffer

    # User Ports ---------------------------------------------------------------
    "user_ports": {
        "wishbone_0" : {
            "type": "wishbone",
        },
    },
}

Please, note that in below logs, all digits are hexadecimals:

Initializing SDRAM @0x1000...
Switching SDRAM to software control.
Switching SDRAM to software control.
Write leveling:
  tCK equivalent taps: 0
  Cmd/Clk scan (0-0
  || best: ffffffff
  Setting Cmd/Clk delay to ffffffff taps.
  Data scan:
  m0: |00000000000000000000000000000000| delay: -
  m0: |00000000000000000000000000000000| delay: -
  m0: |00000000000000000000000000000000| delay: -
  m0: |00000000000000000000000000000000| delay: -
Write latency calibration:
m0:0 m1:0 m2:0 m3:0
Write DQ-DQS training:
m0: |000000000000000000000000000000000| delays: -
m1: |000000000000000000000000000000000| delays: -
m2: |000000000000000000000000000000000| delays: -
m3: |000000000000000000000000000000000| delays: -
Read leveling:
  m0, b0: |00000000000000000000000000000000| delays: -
  m0, b1: |00000000000000000000000000000000| delays: -
  m0, b2: |00000000000000000000000000000000| delays: -
  m0, b3: |00000000000000000000000000000000| delays: -
  m0, b4: |00000000000000000000000000000000| delays: -
  m0, b5: |00000000000000000000000000000000| delays: -
  m0, b6: |00000000000000000000000000000000| delays: -
  m0, b7: |00000000000000000000000000000000| delays: -
  best: m0, b0 delays: -
  m1, b0: |00000000000000000000000000000000| delays: -
  m1, b1: |00000000000000000000000000000000| delays: -
  m1, b2: |00000000000000000000000000000000| delays: -
  m1, b3: |00000000000000000000000000000000| delays: -
  m1, b4: |00000000000000000000000000000000| delays: -
  m1, b5: |00000000000000000000000000000000| delays: -
  m1, b6: |00000000000000000000000000000000| delays: -
  m1, b7: |00000000000000000000000000000000| delays: -
  best: m1, b0 delays: -
  m2, b0: |00000000000000000000000000000000| delays: -
  m2, b1: |00000000000000000000000000000000| delays: -
  m2, b2: |00000000000000000000000000000000| delays: -
  m2, b3: |00000000000000000000000000000000| delays: -
  m2, b4: |00000000000000000000000000000000| delays: -
  m2, b5: |00000000000000000000000000000000| delays: -
  m2, b6: |00000000000000000000000000000000| delays: -
  m2, b7: |00000000000000000000000000000000| delays: -
  best: m2, b0 delays: -
  m3, b0: |00000000000000000000000000000000| delays: -
  m3, b1: |00000000000000000000000000000000| delays: -
  m3, b2: |00000000000000000000000000000000| delays: -
  m3, b3: |00000000000000000000000000000000| delays: -
  m3, b4: |00000000000000000000000000000000| delays: -
  m3, b5: |00000000000000000000000000000000| delays: -
  m3, b6: |00000000000000000000000000000000| delays: -
  m3, b7: |00000000000000000000000000000000| delays: -
  best: m3, b0 delays: -
Switching SDRAM to hardware control.
Switching SDRAM to hardware control.
Initializing SDRAM @0x1000...
Switching SDRAM to software control.
Switching SDRAM to software control.
Write leveling:
  tCK equivalent taps: 0
  Cmd/Clk scan (0-0
  || best: ffffffff
  Setting Cmd/Clk delay to ffffffff taps.
  Data scan:
  m0: |00000000000000000000000000000000| delay: -
  m0: |00000000000000000000000000000000| delay: -
  m0: |00000000000000000000000000000000| delay: -
  m0: |00000000000000000000000000000000| delay: -
Write latency calibration:
m0:0 m1:0 m2:0 m3:0
Write DQ-DQS training:
m0: |000000000000000000000000000000000| delays: -
m1: |000000000000000000000000000000000| delays: -
m2: |000000000000000000000000000000000| delays: -
m3: |000000000000000000000000000000000| delays: -
Read leveling:
  m0, b0: |00000000000000000000000000000000| delays: -
  m0, b1: |00000000000000000000000000000000| delays: -
  m0, b2: |00000000000000000000000000000000| delays: -
  m0, b3: |00000000000000000000000000000000| delays: -
  m0, b4: |00000000000000000000000000000000| delays: -
  m0, b5: |00000000000000000000000000000000| delays: -
  m0, b6: |00000000000000000000000000000000| delays: -
  m0, b7: |00000000000000000000000000000000| delays: -
  best: m0, b0 delays: -
  m1, b0: |00000000000000000000000000000000| delays: -
  m1, b1: |00000000000000000000000000000000| delays: -
  m1, b2: |00000000000000000000000000000000| delays: -
  m1, b3: |00000000000000000000000000000000| delays: -
  m1, b4: |00000000000000000000000000000000| delays: -
  m1, b5: |00000000000000000000000000000000| delays: -
  m1, b6: |00000000000000000000000000000000| delays: -
  m1, b7: |00000000000000000000000000000000| delays: -
  best: m1, b0 delays: -
  m2, b0: |00000000000000000000000000000000| delays: -
  m2, b1: |00000000000000000000000000000000| delays: -
  m2, b2: |00000000000000000000000000000000| delays: -
  m2, b3: |00000000000000000000000000000000| delays: -
  m2, b4: |00000000000000000000000000000000| delays: -
  m2, b5: |00000000000000000000000000000000| delays: -
  m2, b6: |00000000000000000000000000000000| delays: -
  m2, b7: |00000000000000000000000000000000| delays: -
  best: m2, b0 delays: -
  m3, b0: |00000000000000000000000000000000| delays: -
  m3, b1: |00000000000000000000000000000000| delays: -
  m3, b2: |00000000000000000000000000000000| delays: -
  m3, b3: |00000000000000000000000000000000| delays: -
  m3, b4: |00000000000000000000000000000000| delays: -
  m3, b5: |00000000000000000000000000000000| delays: -
  m3, b6: |00000000000000000000000000000000| delays: -
  m3, b7: |00000000000000000000000000000000| delays: -
  best: m3, b0 delays: -
Switching SDRAM to hardware control.
Switching SDRAM to hardware control.
fontamsoc commented 2 years ago

Litedram has been instantiated as follow using a 200 Mhz clock.

litedram litedram (

     .rst (ram_rst_w)

    ,.clk (clk200mhz_w)

    ,.pll_locked (litedram_pll_locked)
    ,.init_done  (litedram_init_done)
    ,.init_error (litedram_init_error)

    ,.ddram_a       (ddr3_addr)
    ,.ddram_ba      (ddr3_ba)
    ,.ddram_ras_n   (ddr3_ras_n)
    ,.ddram_cas_n   (ddr3_cas_n)
    ,.ddram_we_n    (ddr3_we_n)
    ,.ddram_cs_n    (ddr3_cs_n)
    ,.ddram_dm      (ddr3_dm)
    ,.ddram_dq      (ddr3_dq)
    ,.ddram_dqs_p   (ddr3_dqs_p)
    ,.ddram_dqs_n   (ddr3_dqs_n)
    ,.ddram_clk_p   (ddr3_ck_p)
    ,.ddram_clk_n   (ddr3_ck_n)
    ,.ddram_cke     (ddr3_cke)
    ,.ddram_odt     (ddr3_odt)
    ,.ddram_reset_n (ddr3_reset_n)

    ,.user_clk                   (wb4_clk_user_port_w)
    ,.user_rst                   (wb4_rst_user_port_w)
    ,.user_port_wishbone_0_adr   (wb4_addr_user_port_w[LITEDRAM_ARCHBITSZ -1 : clog2(LITEDRAM_ARCHBITSZ/8)])
    ,.user_port_wishbone_0_dat_w (wb4_data_user_port_w0)
    ,.user_port_wishbone_0_dat_r (wb4_data_user_port_w1)
    ,.user_port_wishbone_0_sel   (wb4_sel_user_port_w)
    ,.user_port_wishbone_0_cyc   (wb4_cyc_user_port_w)
    ,.user_port_wishbone_0_stb   (wb4_stb_user_port_w)
    ,.user_port_wishbone_0_ack   (wb4_ack_user_port_w)
    ,.user_port_wishbone_0_we    (wb4_we_user_port_w)

    ,.wb_ctrl_adr   (wb4_addr_wb_ctrl_w[ARCHBITSZ -1 : clog2(ARCHBITSZ/8)])
    ,.wb_ctrl_dat_w (wb4_data_wb_ctrl_w0)
    ,.wb_ctrl_dat_r (wb4_data_wb_ctrl_w1)
    ,.wb_ctrl_sel   (wb4_sel_wb_ctrl_w)
    ,.wb_ctrl_cyc   (wb4_cyc_wb_ctrl_w)
    ,.wb_ctrl_stb   (wb4_stb_wb_ctrl_w)
    ,.wb_ctrl_ack   (wb4_ack_wb_ctrl_w)
    ,.wb_ctrl_we    (wb4_we_wb_ctrl_w)
    ,.wb_ctrl_cti   (3'b000)
    ,.wb_ctrl_bte   (2'b00)
);
fontamsoc commented 2 years ago

Snippet of constraint file:

## Micron MT41J256M16HA-107 DDR3 SDRAM
set_property -dict { PACKAGE_PIN AD3  IOSTANDARD SSTL15_T_DCI   SLEW FAST   VCCAUX_IO HIGH } [get_ports { ddr3_dq[0] }];
set_property -dict { PACKAGE_PIN AC2  IOSTANDARD SSTL15_T_DCI   SLEW FAST   VCCAUX_IO HIGH } [get_ports { ddr3_dq[1] }];
set_property -dict { PACKAGE_PIN AC1  IOSTANDARD SSTL15_T_DCI   SLEW FAST   VCCAUX_IO HIGH } [get_ports { ddr3_dq[2] }];
set_property -dict { PACKAGE_PIN AC5  IOSTANDARD SSTL15_T_DCI   SLEW FAST   VCCAUX_IO HIGH } [get_ports { ddr3_dq[3] }];
set_property -dict { PACKAGE_PIN AC4  IOSTANDARD SSTL15_T_DCI   SLEW FAST   VCCAUX_IO HIGH } [get_ports { ddr3_dq[4] }];
set_property -dict { PACKAGE_PIN AD6  IOSTANDARD SSTL15_T_DCI   SLEW FAST   VCCAUX_IO HIGH } [get_ports { ddr3_dq[5] }];
set_property -dict { PACKAGE_PIN AE6  IOSTANDARD SSTL15_T_DCI   SLEW FAST   VCCAUX_IO HIGH } [get_ports { ddr3_dq[6] }];
set_property -dict { PACKAGE_PIN AC7  IOSTANDARD SSTL15_T_DCI   SLEW FAST   VCCAUX_IO HIGH } [get_ports { ddr3_dq[7] }];
set_property -dict { PACKAGE_PIN AF2  IOSTANDARD SSTL15_T_DCI   SLEW FAST   VCCAUX_IO HIGH } [get_ports { ddr3_dq[8] }];
set_property -dict { PACKAGE_PIN AE1  IOSTANDARD SSTL15_T_DCI   SLEW FAST   VCCAUX_IO HIGH } [get_ports { ddr3_dq[9] }];
set_property -dict { PACKAGE_PIN AF1  IOSTANDARD SSTL15_T_DCI   SLEW FAST   VCCAUX_IO HIGH } [get_ports { ddr3_dq[10] }];
set_property -dict { PACKAGE_PIN AE4  IOSTANDARD SSTL15_T_DCI   SLEW FAST   VCCAUX_IO HIGH } [get_ports { ddr3_dq[11] }];
set_property -dict { PACKAGE_PIN AE3  IOSTANDARD SSTL15_T_DCI   SLEW FAST   VCCAUX_IO HIGH } [get_ports { ddr3_dq[12] }];
set_property -dict { PACKAGE_PIN AE5  IOSTANDARD SSTL15_T_DCI   SLEW FAST   VCCAUX_IO HIGH } [get_ports { ddr3_dq[13] }];
set_property -dict { PACKAGE_PIN AF5  IOSTANDARD SSTL15_T_DCI   SLEW FAST   VCCAUX_IO HIGH } [get_ports { ddr3_dq[14] }];
set_property -dict { PACKAGE_PIN AF6  IOSTANDARD SSTL15_T_DCI   SLEW FAST   VCCAUX_IO HIGH } [get_ports { ddr3_dq[15] }];
set_property -dict { PACKAGE_PIN AJ4  IOSTANDARD SSTL15_T_DCI   SLEW FAST   VCCAUX_IO HIGH } [get_ports { ddr3_dq[16] }];
set_property -dict { PACKAGE_PIN AH6  IOSTANDARD SSTL15_T_DCI   SLEW FAST   VCCAUX_IO HIGH } [get_ports { ddr3_dq[17] }];
set_property -dict { PACKAGE_PIN AH5  IOSTANDARD SSTL15_T_DCI   SLEW FAST   VCCAUX_IO HIGH } [get_ports { ddr3_dq[18] }];
set_property -dict { PACKAGE_PIN AH2  IOSTANDARD SSTL15_T_DCI   SLEW FAST   VCCAUX_IO HIGH } [get_ports { ddr3_dq[19] }];
set_property -dict { PACKAGE_PIN AJ2  IOSTANDARD SSTL15_T_DCI   SLEW FAST   VCCAUX_IO HIGH } [get_ports { ddr3_dq[20] }];
set_property -dict { PACKAGE_PIN AJ1  IOSTANDARD SSTL15_T_DCI   SLEW FAST   VCCAUX_IO HIGH } [get_ports { ddr3_dq[21] }];
set_property -dict { PACKAGE_PIN AK1  IOSTANDARD SSTL15_T_DCI   SLEW FAST   VCCAUX_IO HIGH } [get_ports { ddr3_dq[22] }];
set_property -dict { PACKAGE_PIN AJ3  IOSTANDARD SSTL15_T_DCI   SLEW FAST   VCCAUX_IO HIGH } [get_ports { ddr3_dq[23] }];
set_property -dict { PACKAGE_PIN AF7  IOSTANDARD SSTL15_T_DCI   SLEW FAST   VCCAUX_IO HIGH } [get_ports { ddr3_dq[24] }];
set_property -dict { PACKAGE_PIN AG7  IOSTANDARD SSTL15_T_DCI   SLEW FAST   VCCAUX_IO HIGH } [get_ports { ddr3_dq[25] }];
set_property -dict { PACKAGE_PIN AJ6  IOSTANDARD SSTL15_T_DCI   SLEW FAST   VCCAUX_IO HIGH } [get_ports { ddr3_dq[26] }];
set_property -dict { PACKAGE_PIN AK6  IOSTANDARD SSTL15_T_DCI   SLEW FAST   VCCAUX_IO HIGH } [get_ports { ddr3_dq[27] }];
set_property -dict { PACKAGE_PIN AJ8  IOSTANDARD SSTL15_T_DCI   SLEW FAST   VCCAUX_IO HIGH } [get_ports { ddr3_dq[28] }];
set_property -dict { PACKAGE_PIN AK8  IOSTANDARD SSTL15_T_DCI   SLEW FAST   VCCAUX_IO HIGH } [get_ports { ddr3_dq[29] }];
set_property -dict { PACKAGE_PIN AK5  IOSTANDARD SSTL15_T_DCI   SLEW FAST   VCCAUX_IO HIGH } [get_ports { ddr3_dq[30] }];
set_property -dict { PACKAGE_PIN AK4  IOSTANDARD SSTL15_T_DCI   SLEW FAST   VCCAUX_IO HIGH } [get_ports { ddr3_dq[31] }];
set_property -dict { PACKAGE_PIN AD4  IOSTANDARD SSTL15   SLEW FAST   VCCAUX_IO HIGH } [get_ports { ddr3_dm[0] }];
set_property -dict { PACKAGE_PIN AF3  IOSTANDARD SSTL15   SLEW FAST   VCCAUX_IO HIGH } [get_ports { ddr3_dm[1] }];
set_property -dict { PACKAGE_PIN AH4  IOSTANDARD SSTL15   SLEW FAST   VCCAUX_IO HIGH } [get_ports { ddr3_dm[2] }];
set_property -dict { PACKAGE_PIN AF8  IOSTANDARD SSTL15   SLEW FAST   VCCAUX_IO HIGH } [get_ports { ddr3_dm[3] }];
set_property -dict { PACKAGE_PIN AD2  IOSTANDARD DIFF_SSTL15_T_DCI   SLEW FAST   VCCAUX_IO HIGH } [get_ports { ddr3_dqs_p[0] }];
set_property -dict { PACKAGE_PIN AD1  IOSTANDARD DIFF_SSTL15_T_DCI   SLEW FAST   VCCAUX_IO HIGH } [get_ports { ddr3_dqs_n[0] }];
set_property -dict { PACKAGE_PIN AG4  IOSTANDARD DIFF_SSTL15_T_DCI   SLEW FAST   VCCAUX_IO HIGH } [get_ports { ddr3_dqs_p[1] }];
set_property -dict { PACKAGE_PIN AG3  IOSTANDARD DIFF_SSTL15_T_DCI   SLEW FAST   VCCAUX_IO HIGH } [get_ports { ddr3_dqs_n[1] }];
set_property -dict { PACKAGE_PIN AG2  IOSTANDARD DIFF_SSTL15_T_DCI   SLEW FAST   VCCAUX_IO HIGH } [get_ports { ddr3_dqs_p[2] }];
set_property -dict { PACKAGE_PIN AH1  IOSTANDARD DIFF_SSTL15_T_DCI   SLEW FAST   VCCAUX_IO HIGH } [get_ports { ddr3_dqs_n[2] }];
set_property -dict { PACKAGE_PIN AH7  IOSTANDARD DIFF_SSTL15_T_DCI   SLEW FAST   VCCAUX_IO HIGH } [get_ports { ddr3_dqs_p[3] }];
set_property -dict { PACKAGE_PIN AJ7  IOSTANDARD DIFF_SSTL15_T_DCI   SLEW FAST   VCCAUX_IO HIGH } [get_ports { ddr3_dqs_n[3] }];
set_property -dict { PACKAGE_PIN AH9  IOSTANDARD SSTL15   SLEW FAST   VCCAUX_IO HIGH } [get_ports { ddr3_addr[14] }];
set_property -dict { PACKAGE_PIN AA12 IOSTANDARD SSTL15   SLEW FAST   VCCAUX_IO HIGH } [get_ports { ddr3_addr[13] }];
set_property -dict { PACKAGE_PIN AB12 IOSTANDARD SSTL15   SLEW FAST   VCCAUX_IO HIGH } [get_ports { ddr3_addr[12] }];
set_property -dict { PACKAGE_PIN AA8  IOSTANDARD SSTL15   SLEW FAST   VCCAUX_IO HIGH } [get_ports { ddr3_addr[11] }];
set_property -dict { PACKAGE_PIN AB8  IOSTANDARD SSTL15   SLEW FAST   VCCAUX_IO HIGH } [get_ports { ddr3_addr[10] }];
set_property -dict { PACKAGE_PIN Y11  IOSTANDARD SSTL15   SLEW FAST   VCCAUX_IO HIGH } [get_ports { ddr3_addr[9] }];
set_property -dict { PACKAGE_PIN Y10  IOSTANDARD SSTL15   SLEW FAST   VCCAUX_IO HIGH } [get_ports { ddr3_addr[8] }];
set_property -dict { PACKAGE_PIN AA11 IOSTANDARD SSTL15   SLEW FAST   VCCAUX_IO HIGH } [get_ports { ddr3_addr[7] }];
set_property -dict { PACKAGE_PIN AA10 IOSTANDARD SSTL15   SLEW FAST   VCCAUX_IO HIGH } [get_ports { ddr3_addr[6] }];
set_property -dict { PACKAGE_PIN AA13 IOSTANDARD SSTL15   SLEW FAST   VCCAUX_IO HIGH } [get_ports { ddr3_addr[5] }];
set_property -dict { PACKAGE_PIN AD9  IOSTANDARD SSTL15   SLEW FAST   VCCAUX_IO HIGH } [get_ports { ddr3_addr[4] }];
set_property -dict { PACKAGE_PIN AC10 IOSTANDARD SSTL15   SLEW FAST   VCCAUX_IO HIGH } [get_ports { ddr3_addr[3] }];
set_property -dict { PACKAGE_PIN AD8  IOSTANDARD SSTL15   SLEW FAST   VCCAUX_IO HIGH } [get_ports { ddr3_addr[2] }];
set_property -dict { PACKAGE_PIN AE8  IOSTANDARD SSTL15   SLEW FAST   VCCAUX_IO HIGH } [get_ports { ddr3_addr[1] }];
set_property -dict { PACKAGE_PIN AC12 IOSTANDARD SSTL15   SLEW FAST   VCCAUX_IO HIGH } [get_ports { ddr3_addr[0] }];
set_property -dict { PACKAGE_PIN AC11 IOSTANDARD SSTL15   SLEW FAST   VCCAUX_IO HIGH } [get_ports { ddr3_ba[2] }];
set_property -dict { PACKAGE_PIN AB10 IOSTANDARD SSTL15   SLEW FAST   VCCAUX_IO HIGH } [get_ports { ddr3_ba[1] }];
set_property -dict { PACKAGE_PIN AE9  IOSTANDARD SSTL15   SLEW FAST   VCCAUX_IO HIGH } [get_ports { ddr3_ba[0] }];
set_property -dict { PACKAGE_PIN AB9  IOSTANDARD DIFF_SSTL15   SLEW FAST   VCCAUX_IO HIGH } [get_ports { ddr3_ck_p }];
set_property -dict { PACKAGE_PIN AC9  IOSTANDARD DIFF_SSTL15   SLEW FAST   VCCAUX_IO HIGH } [get_ports { ddr3_ck_n }];
set_property -dict { PACKAGE_PIN AE11 IOSTANDARD SSTL15   SLEW FAST   VCCAUX_IO HIGH } [get_ports { ddr3_ras_n }];
set_property -dict { PACKAGE_PIN AF11 IOSTANDARD SSTL15   SLEW FAST   VCCAUX_IO HIGH } [get_ports { ddr3_cas_n }];
set_property -dict { PACKAGE_PIN AG13 IOSTANDARD SSTL15   SLEW FAST   VCCAUX_IO HIGH } [get_ports { ddr3_we_n }];
set_property -dict { PACKAGE_PIN AJ9  IOSTANDARD SSTL15   SLEW FAST   VCCAUX_IO HIGH } [get_ports { ddr3_cke }];
set_property -dict { PACKAGE_PIN AK9  IOSTANDARD SSTL15   SLEW FAST   VCCAUX_IO HIGH } [get_ports { ddr3_odt }];
set_property -dict { PACKAGE_PIN AH12 IOSTANDARD SSTL15   SLEW FAST   VCCAUX_IO HIGH } [get_ports { ddr3_cs_n }];
set_property -dict { PACKAGE_PIN AG5  IOSTANDARD SSTL15   SLEW FAST   VCCAUX_IO HIGH } [get_ports { ddr3_reset_n }];
set_property INTERNAL_VREF 0.750 [get_iobanks 34]

set_property CONFIG_VOLTAGE 3.3 [current_design]
set_property CFGBVS VCCO [current_design]

set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design];
set_property BITSTREAM.CONFIG.CONFIGRATE 33 [current_design];
set_property CONFIG_MODE SPIx4 [current_design];
fontamsoc commented 2 years ago

Downgraded to:

//--------------------------------------------------------------------------------
// Migen (7014bdc) & LiteX (75134605) on 2022-03-15 18:59:15
//--------------------------------------------------------------------------------

using

for i in $(ls); do (cd $i && git checkout 'HEAD@{Feb 19 2021}'); done;

I downgraded because Litedram was no longer working with NexysVideo, and Nexys4DDR was not always working.

The downgrade has both Nexys4DDR and NexysVideo working, but Genesys2 still does not work.

Below is the initialization output on Genesys2 using downgraded code:

Initializing SDRAM @ 0x1000
Switching SDRAM to software control.
Write leveling:
  tCK/4 taps: 8
  Cmd/Clk scan (0-10
  |1111111000000000| best: 0
  Setting Cmd/Clk delay to 0 taps.
  Data scan:
  m0: |000000000000000000000000| delay: 0
  m0: |000000000000000000000000| delay: 0
  m0: |000000000000000000000000| delay: 0
  m0: |000000000000000000000000| delay: 0
Write latency calibration:
m0:- m1:- m2:- m3:-
Read leveling:
  m0, b0: |00000000000000000000000000000000| delays: -
  m0, b1: |00000000000000000000000000000000| delays: -
  m0, b2: |00000000000000000000000000000000| delays: -
  m0, b3: |00000000000000000000000000000000| delays: -
  m0, b4: |00000000000000000000000000000000| delays: -
  m0, b5: |00000000000000000000000000000000| delays: -
  m0, b6: |00000000000000000000000000000000| delays: -
  m0, b7: |00000000000000000000000000000000| delays: -
  best: m0, b0 delays: -
  m1, b0: |00000000000000000000000000000000| delays: -
  m1, b1: |00000000000000000000000000000000| delays: -
  m1, b2: |00000000000000000000000000000000| delays: -
  m1, b3: |00000000000000000000000000000000| delays: -
  m1, b4: |00000000000000000000000000000000| delays: -
  m1, b5: |00000000000000000000000000000000| delays: -
  m1, b6: |00000000000000000000000000000000| delays: -
  m1, b7: |00000000000000000000000000000000| delays: -
  best: m1, b0 delays: -
  m2, b0: |00000000000000000000000000000000| delays: -
  m2, b1: |00000000000000000000000000000000| delays: -
  m2, b2: |00000000000000000000000000000000| delays: -
  m2, b3: |00000000000000000000000000000000| delays: -
  m2, b4: |00000000000000000000000000000000| delays: -
  m2, b5: |00000000000000000000000000000000| delays: -
  m2, b6: |00000000000000000000000000000000| delays: -
  m2, b7: |00000000000000000000000000000000| delays: -
  best: m2, b0 delays: -
  m3, b0: |00000000000000000000000000000000| delays: -
  m3, b1: |00000000000000000000000000000000| delays: -
  m3, b2: |00000000000000000000000000000000| delays: -
  m3, b3: |00000000000000000000000000000000| delays: -
  m3, b4: |00000000000000000000000000000000| delays: -
  m3, b5: |00000000000000000000000000000000| delays: -
  m3, b6: |00000000000000000000000000000000| delays: -
  m3, b7: |00000000000000000000000000000000| delays: -
  best: m3, b0 delays: -
Switching SDRAM to hardware control.
fontamsoc commented 2 years ago

what is the unit of cdelay() argument used by SDRAM initialization code ? Currently I am assuming clock-cycles, with a frequency of 100Mhz on Genesys2.

fontamsoc commented 2 years ago

Get sources using:

git clone https://github.com/fontamsoc/hw.git
git checkout pu32_genesys2_dev

Everything specific to genesys2 are found under pu32-genesys2/: https://github.com/fontamsoc/hw/tree/pu32_genesys2_dev/pu32-genesys2 Find the bitstream at pu32-genesys2/genesys2.bit or regenerate it from Vivado using project file pu32-genesys2/vivado2020/genesys2.xpr.

The LiteDRAM sources are found under pu32-genesys2/litedram/; They are pretty much the same as the originals at litex/soc/software/liblitedram/sdram.c with the difference that all printf() have been replaced by puts() and all values are printed in hexadecimal. Also find the LiteDRAM generated files that are csr.h sdram_phy.h soc.h. To rebuild LiteDRAM initialization program, run make -C pu32-genesys2/litedram/; it will generate the litedram.hex which is used by Vivado when synthesizing to genesys2.bit.

An SD-Card is needed to run the project. Find the SD-Card image at pu32-genesys2/memtest.img which can be flashed using either dd if=pu32-vmlinux.img of=/dev/<sdx> bs=1M oflag=sync status=progress or BalenaEtcher.

The image contains a memory test program, which will execute if LiteDRAM correctly initializes, and show something like this:

soc  1bb66160
bios fc731125
kernel loaded
testing 8bits memory accesses
f2
fontamsoc commented 2 years ago

xdc files was missing create_clock both clk200mhz_p and clk200mhz_n.

create_clock -period 5 -waveform {0 2.5} -name clk200mhz_p [get_ports clk200mhz_p]
create_clock -period 5 -waveform {2.5 5} -name clk200mhz_n [get_ports clk200mhz_n]