Strategy steering: Best way to stream data into a custom accelerator when litedram is being used inside Litex SoC?

[francis2tm]

Hello, My goal is to have a litex SoC with a vexriscv CPU and a custom accelerator that constantly consumes memory from an external DDR3. What is the best way to achieve "stream" like dataflow onto the accelerator, considering that the CPU will also be using the DDR3 since all its memory regions reside in the DDR3 (text, data, bss, heap and stack)? Essentially the accelerator will have priority for everything since it's okay to sacrifice CPU's performance. My first approach is to connect the accelerator to the wishbone bus via a DMA. However, this would mean that the CPU would race with DMA for the BUS pretty much all the time. Is there a way to get more "direct" connection to liteDRAM and thus improve accelerator's performance?

Thanks in advance

[enjoy-digital]

Hi @francis2tm,

you can get additional direct ports with LiteDRAM with self.sdram.crossbar.get_port() and can then use them with Native, AXI or Wishbone interfaces, so you could just create a such port and connect your accelerator to it. Since memory will be shared, you'll just have to be careful to split the DDR3 in regions: One for the CPU, the other for the Accelerator.

[francis2tm]

Thanks for the fast reply @enjoy-digital, 1) Do you think is the way that produces best performance for the accelerator? As opposed the accelerator + DMA connected to wishbone bus alongside CPU and other peripherals. If so, why? 2) liteDRAM can manage 2 ports (1 Wishbone to interact with litex SoC and 1 native to interact with accelerator) without additional control?

[enjoy-digital]

This will provide better performance than connecting the DMAs to the Wishbone bus yes. LiteDRAM will automatically arbitrate the ports yes (with a Round Robin arbiter). It would be possible to add a priority control signal if required.

[francis2tm]

thanks a lot for the info!