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Small footprint and configurable DRAM core
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DDR4 Memtest Failed #305

Closed zhbeiluo closed 2 years ago

zhbeiluo commented 2 years ago

Hi there,

I'm using litedram on Xilinx Zynq UltraScale+ device. My memory cannot work correctly, and I have no clue why this happens. From the output, I find that memread errors always happen in the second byte (e.g., 0x74_df_8545 vs. 0x74_dd_8545). Have anyone ever seen this? Following is my minicom output. 

[1m        __   _ __      _  __
       / /  (_) /____ | |/_/
      / /__/ / __/ -_)>  <
     /____/_/\__/\__/_/|_|
   Build your hardware, easily!

 (c) Copyright 2012-2022 Enjoy-Digital
 (c) Copyright 2007-2015 M-Labs

 BIOS built on Apr 12 2022 10:58:24
 BIOS CRC passed (f58a88ec)

 Migen git sha1: ac70301
 LiteX git sha1: f2240361

--=============== SoC ==================--
CPU:        VexRiscv_Min @ 100MHz
BUS:        WISHBONE 32-bit @ 4GiB
CSR:        32-bit data
ROM:        64KiB
SRAM:       8KiB
SDRAM:      1048576KiB 64-bit @ 800MT/s (CL-9 CWL-9)

--========== Initialization ============--
Initializing SDRAM @0x40000000...
Switching SDRAM to software control.
Write leveling:
  tCK equivalent taps: 704
  Cmd/Clk scan (0-352)
  |000000  |000000000  |000000000  |000000000| best: 100
  Setting Cmd/Clk delay to 100 taps.
  Data scan:
  m0: |000000000000000000000| delay: -
  m1: |111000000000000000000| delay: -
  m2: |111111111111111111111| delay: 00
  m3: |111111100000000000000| delay: -
  m4: |111111111111100000000| delay: 00
  m5: |111111111111111111111| delay: 00
  m6: |111111111111111000000| delay: 00
  m7: |111111111111111111100| delay: 00
Write latency calibration:
m0:0 m1:6 m2:0 m3:6 m4:6 m5:6 m6:6 m7:6 
Read leveling:
  m0, b00: |00000000000000000000000000000000| delays: -
  m0, b01: |00000000000000000000000000000000| delays: -
  m0, b02: |01111111111111111100000000000000| delays: 142+-142
  m0, b03: |00000000000000000000001111111111| delays: 428+-84
  m0, b04: |00000000000000000000000000000000| delays: -
  m0, b05: |00000000000000000000000000000000| delays: -
  m0, b06: |00000000000000000000000000000000| delays: -
  m0, b07: |00000000000000000000000000000000| delays: -
  best: m0, b02 delays: 141+-141
  m1, b00: |00000000000000000000000000000000| delays: -
  m1, b01: |00000000000000000000000000000000| delays: -
  m1, b02: |11111111111111000000000000000000| delays: 109+-109
  m1, b03: |00000000000000000011111111111111| delays: 398+-114
  m1, b04: |00000000000000000000000000000000| delays: -
  m1, b05: |00000000000000000000000000000000| delays: -
  m1, b06: |00000000000000000000000000000000| delays: -
  m1, b07: |00000000000000000000000000000000| delays: -
  best: m1, b03 delays: 398+-113
  m2, b00: |00000000000000000000000000000000| delays: -
  m2, b01: |00000000000000000000000000000000| delays: -
  m2, b02: |00000111111111111111000000000000| delays: 135+-71
  m2, b03: |00000000000000000000000000111111| delays: 462+-50
  m2, b04: |00000000000000000000000000000000| delays: -
  m2, b05: |00000000000000000000000000000000| delays: -
  m2, b06: |00000000000000000000000000000000| delays: -
  m2, b07: |00000000000000000000000000000000| delays: -
  best: m2, b02 delays: 134+-68
  m3, b00: |00000000000000000000000000000000| delays: -
  m3, b01: |00000000000000000000000000000000| delays: -
  m3, b02: |11111111111100000000000000000000| delays: 95+-95
  m3, b03: |00000000000000001111111111111111| delays: 383+-128
  m3, b04: |00000000000000000000000000000000| delays: -
  m3, b05: |00000000000000000000000000000000| delays: -
  m3, b06: |00000000000000000000000000000000| delays: -
  m3, b07: |00000000000000000000000000000000| delays: -
  best: m3, b03 delays: 384+-128
  m4, b00: |00000000000000000000000000000000| delays: -
  m4, b01: |00000000000000000000000000000000| delays: -
  m4, b02: |11111111000000000000000000000000| delays: 62+-62
  m4, b03: |00000000000001111111111111111100| delays: 331+-138
  m4, b04: |00000000000000000000000000000000| delays: -
  m4, b05: |00000000000000000000000000000000| delays: -
  m4, b06: |00000000000000000000000000000000| delays: -
  m4, b07: |00000000000000000000000000000000| delays: -
  best: m4, b03 delays: 331+-136
  m5, b00: |00000000000000000000000000000000| delays: -
  m5, b01: |00000000000000000000000000000000| delays: -
  m5, b02: |00000000000000000000000000000000| delays: -
  m5, b03: |00011111111111111111100000000000| delays: 190+-140
  m5, b04: |00000000000000000000000001111111| delays: 452+-59
  m5, b05: |00000000000000000000000000000000| delays: -
  m5, b06: |00000000000000000000000000000000| delays: -
  m5, b07: |00000000000000000000000000000000| delays: -
  best: m5, b03 delays: 190+-140
  m6, b00: |00000000000000000000000000000000| delays: -
  m6, b01: |00000000000000000000000000000000| delays: -
  m6, b02: |11111000000000000000000000000000| delays: 36+-36
  m6, b03: |00000000011111111111111111100000| delays: 283+-142
  m6, b04: |00000000000000000000000000000001| delays: 501+-11
  m6, b05: |00000000000000000000000000000000| delays: -
  m6, b06: |00000000000000000000000000000000| delays: -
  m6, b07: |00000000000000000000000000000000| delays: -
  best: m6, b03 delays: 282+-141
  m7, b00: |00000000000000000000000000000000| delays: -
  m7, b01: |00000000000000000000000000000000| delays: -
  m7, b02: |11100000000000000000000000000000| delays: 20+-20
  m7, b03: |00000001111111111111111110000000| delays: 246+-143
  m7, b04: |00000000000000000000000000000111| delays: 480+-31
  m7, b05: |00000000000000000000000000000000| delays: -
  m7, b06: |00000000000000000000000000000000| delays: -
  m7, b07: |00000000000000000000000000000000| delays: -
  best: m7, b03 delays: 247+-142
Switching SDRAM to hardware control.
Memtest at 0x40000000 (2.0MiB)...
  Write: 0x40000000-0x40000000 0B     Write: 0x40000000-0x40020000 128.0KiB     Write: 0x40000000-0x40040000 256.0KiB     Write: 0x40000000-0x40060000 384.0KiB     Write: 0x40000000-0x40080000 512.0KiB     Write: 0x40000000-0x400a0000 640.0KiB     Write: 0x40000000-0x400c0000 768.0KiB     Write: 0x40000000-0x400e0000 896.0KiB     Write: 0x40000000-0x40100000 1.0MiB     Write: 0x40000000-0x40120000 1.1MiB     Write: 0x40000000-0x40140000 1.2MiB     Write: 0x40000000-0x40160000 1.3MiB     Write: 0x40000000-0x40180000 1.5MiB     Write: 0x40000000-0x401a0000 1.6MiB     Write: 0x40000000-0x401c0000 1.7MiB     Write: 0x40000000-0x401e0000 1.8MiB     Write: 0x40000000-0x40200000 2.0MiB   
   Read: 0x40000000-0x40000000 0B   memtest_data error @ 0x4000b668: 0x57ef83cc vs 0x57ed83cc
memtest_data error @ 0x4000df20: 0x74ff80e9 vs 0x74fd80e9
   Read: 0x40000000-0x40020000 128.0KiB   @0x40035bf0: Redeemed at 7. attempt
memtest_data error @ 0x4003cee8: 0x5def43c9 vs 0x5daf43c9
@0x4003dc28: Redeemed at 2. attempt
@0x4003ef68: Redeemed at 4. attempt
   Read: 0x40000000-0x40040000 256.0KiB   @0x40059568: Redeemed at 2. attempt
memtest_data error @ 0x4005a5a0: 0x73cf80b2 vs 0x73cd80b2
@0x4005f8f0: Redeemed at 2. attempt
   Read: 0x40000000-0x40060000 384.0KiB   memtest_data error @ 0x40064d68: 0x26ff899e vs 0x26fd899e
@0x4006edf0: Redeemed at 8. attempt
@0x4006fce0: Redeemed at 3. attempt
   Read: 0x40000000-0x40080000 512.0KiB   memtest_data error @ 0x40097168: 0x74ff806e vs 0x74fd806e
memtest_data error @ 0x4009bb68: 0x67ebc27e vs 0x67e9c27e
memtest_data error @ 0x4009f3f0: 0x77ffc163 vs 0x77fdc163
   Read: 0x40000000-0x400a0000 640.0KiB   memtest_data error @ 0x400ab360: 0x76ef855d vs 0x76ed855d
@0x400b7e28: Redeemed at 4. attempt
   Read: 0x40000000-0x400c0000 768.0KiB      Read: 0x40000000-0x400e0000 896.0KiB   @0x400f5fa0: Redeemed at 2. attempt
@0x400faaf0: Redeemed at 2. attempt
@0x400fb368: Redeemed at 5. attempt
@0x400fff68: Redeemed at 2. attempt
   Read: 0x40000000-0x40100000 1.0MiB   memtest_data error @ 0x4011df68: 0x74df8545 vs 0x74dd8545
   Read: 0x40000000-0x40120000 1.1MiB   memtest_data error @ 0x40137fa8: 0x5def03f1 vs 0x5daf03f1
   Read: 0x40000000-0x40140000 1.2MiB   memtest_data error @ 0x40146760: 0x5ae681c4 vs 0x5aa681c4
memtest_data error @ 0x40147f70: 0x379f83e9 vs 0x379d83e9
   Read: 0x40000000-0x40160000 1.3MiB   @0x40165128: Redeemed at 7. attempt
@0x401672e0: Redeemed at 6. attempt
   Read: 0x40000000-0x40180000 1.5MiB      Read: 0x40000000-0x401a0000 1.6MiB   @0x401a4fe8: Redeemed at 2. attempt
   Read: 0x40000000-0x401c0000 1.7MiB      Read: 0x40000000-0x401e0000 1.8MiB      Read: 0x40000000-0x40200000 2.0MiB   
  bus errors:  0/256
  addr errors: 0/8192
  data errors: 13/524288
Memtest KO
Memory initialization failed

--============= Console ================--

litex> 
litex> 
litex> 
litex> 
litex> ^[  

I am wondering if there are some debugs methods to debug this problem. Thanks in advance.

enjoy-digital commented 2 years ago

Hi @zhbeiluo,

can you first increase frequency to at least 125MHz? If not helping, the issue could be related to constraints or electrical settings. First be sure to have the INTERNAL_VREF constraints applied to the DRAM banks in your platform file (ex: https://github.com/litex-hub/litex-boards/blob/master/litex_boards/platforms/xilinx_zcu104.py#L121-L123) If you share your target/platform, I could do some checks.

You can also use ddr4_mr_gen tool to modify the electrical settings. Just run the script with the right parameters, copy/paste the commands in the BIOS and do a sdram_calfollowed by asdram_test.

zhbeiluo commented 2 years ago

@enjoy-digital thanks!

After adding INTERNAL_VREF constraints, it worked.

enjoy-digital commented 2 years ago

Great!