Open machdyne opened 2 years ago
I mashed together the code from HalfRateGENSDRPHY and S6QuarterRateDDRPHY, and it's not working, the memtest fails, but maybe somebody can tell me where I'm going wrong?
https://github.com/machdyne/litedram/commit/f9da309ed41c9b0bf726c12a18f53d235c61a547
Your best bet is to make a PR of your changes to this repo that makes it easier to look at the diff and will (hopefully) be merged.
I'm trying to implement a Quarter-rate Generic SDR PHY module so that I can run a CPU at 40MHz with the SDRAM at 160MHz. It looked straight-forward at first but I don't really know what I'm doing and haven't had much success. If anyone could provide any tips or examples of how to implement this it would be appreciated.