Typical litedram-L2 port sizes

[bala122]

Hi, @mithro and anyone else, I just wanted to know what the typical litedram port sizes are ( in bits I presume) since I need to figure out the L2 size synthesized by litex implemented for the arty A7 100t board. Normally, the shared L2 size is given by:

            # Request a LiteDRAM native port. 
             port = sdram.crossbar.get_port() 
             port.data_width = 2**int(log2(port.data_width)) # Round to nearest power of 2. 

             # Create Wishbone Slave. 
             wb_sdram = wishbone.Interface() 
             self.bus.add_slave("main_ram", wb_sdram) 

             # L2 Cache 
             if l2_cache_size != 0: 
                 # Insert L2 cache inbetween Wishbone bus and LiteDRAM 
                 l2_cache_size = max(l2_cache_size, int(2*port.data_width/8)) # Use minimal size if lower

So, if I give an L2 size of say 64 or 256 bytes, will it be the same as the input or is the determined by the port width Please let me know about this soon Thanks, Bala.