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enjoy-digital / litedram

Small footprint and configurable DRAM core
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submodules verilog #316

Open CarrolXC opened 1 year ago

CarrolXC commented 1 year ago

Hi , I am generating verilog file through gen.py and I did see a top level verilog file in the "build" folder. However , I found I missed all the submodules used in the top level, like "BUFG"or "IOBUF" which I could trace to some other python file.Does anyone have ideas on how to generate all the verilog files needed including all the submodules.Sincerely appreciate any suggestion!

smosanu commented 1 year ago

Some submodules like "BUFG" or "IOBUF" are specific to the tools for the board you use (in this case I assume it is the Xilinx tools?) and you shouldn't need to Verilog code for them...

enjoy-digital commented 1 year ago

Hi @CarrolXC,

these primitives are indeed Xilinx's primitives with models available in Unisim: https://github.com/Xilinx/XilinxUnisimLibrary. You'll be able to simulate them with Xilinx simulator of by also compiling these models with your simulator (should work with iverilog, would need to be tested with Verilator).