DMA AXI BUG

[mohammadshahidzade]

Hi, I believe that you have not updated the axis connection of DMA and it is not working. When I try to connect it to the axis it gives me an error like this.

  File "litex_sim.py", line 1259, in <module>
    main()
  File "litex_sim.py", line 1219, in main
    soc = SimSoC(
  File "litex_sim.py", line 248, in __init__
    self.submodules.mm2s = mm2s = LiteDRAMDMAReader(axi_port_mm2s,fifo_buffered=True,with_csr=True)
  File "/home/mohammad/Desktop/fpga_dnn/litex/litedram/litedram/frontend/dma.py", line 107, in __init__
    rdata.connect(fifo.sink, omit={"id", "resp"}),
  File "/home/mohammad/Desktop/fpga_dnn/litex/migen/migen/genlib/record.py", line 165, in connect
    r += self_e.connect(getattr(slave, field), keep=keep, omit=omit)
  File "/home/mohammad/Desktop/fpga_dnn/litex/migen/migen/genlib/record.py", line 158, in connect
    r += [getattr(slave, field).eq(self_e) for slave in slaves]
  File "/home/mohammad/Desktop/fpga_dnn/litex/migen/migen/genlib/record.py", line 158, in <listcomp>
    r += [getattr(slave, field).eq(self_e) for slave in slaves]
AttributeError: 'Record' object has no attribute 'dest'

Then, I changed "dma.py" line 107 to rdata.connect(fifo.sink, omit={"id","resp","dest","user"}). it is working now, but it gives me a wrong answer so I believe there is more to it than adding,"dest","user". When I looked at the waveforms it was giving me all zeros not sure where the problem is. Here is my code:

user_port_mm2s = self.sdram.crossbar.get_port(data_width=sdram_data_width)
axi_port_mm2s  = LiteDRAMAXIPort(
    data_width    = user_port_mm2s.data_width,
    address_width = user_port_mm2s.address_width + log2_int(user_port_mm2s.data_width//8),
    id_width      = 1)
axi2native_mm2s = LiteDRAMAXI2Native(
    port  = user_port_mm2s,
    axi  = axi_port_mm2s,
    # with_read_modify_write = port.get("ecc", False)
)
self.submodules += axi2native_mm2s 
self.submodules.mm2s = mm2s = LiteDRAMDMAReader(axi_port_mm2s,with_csr=True)
self.add_csr("mm2s")

it also works correctly when I make a native connection like this: self.submodules.mm2s = mm2s = LiteDRAMDMAReader(user_port_mm2s,with_csr=True)

[enjoy-digital]

Thanks @mohammadshahidzade for reporting, as discussed in https://github.com/enjoy-digital/litex/issues/1557, this has been fixed by https://github.com/enjoy-digital/litedram/commit/d95c1fc5838de0dafe196ab89d5c6ce1de38105d.