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enjoy-digital / litedram

Small footprint and configurable DRAM core
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Need Help Generating Verilog DRAM controller, while maininting module hiraerachies. #324

Closed dinaabdelbaky closed 1 year ago

dinaabdelbaky commented 1 year ago

Hi, While trying litedram_gen the generated RTL was a top module and didn't maintain the hierarchy of the submodules. Is there a way that I can generate the RTL while having submodules ex (AXI2NAtive, Wishbone, DFI, PHY, Core). I want to modify in the generated RTL, and lack of hierarchy makes it a bit difficult for modification and debugging. Kind Regards

enjoy-digital commented 1 year ago

Hi @dinaabdelbaky,

this is not yet possible. The design is generated with a flat hierarchy but there are plans to allow it in the future.