Carrying out the LiteDRAM standalone core initialization manually, through wishbone ctrl interface

[dinaabdelbaky]

Hi, I am new to the liteDRAM. I generated the core in a standalone mode, targeting Artix device, I also generated the corr. csv containing the csr addresses. I am using the core with Micron DDR3 model and a testbench to carryout some simulations and explorations of memory operations. I checked out the generated sdram_phy.h it includes init_sequence, I tried to carry out the above sequence by writing to the corresponding csr registers. However, I didn't see anything happening on the DFI interface or the memory interface. Please point out what I am missing. P.S: I have seen some similar questions, and some of the answers points out to writing data from an init file, but I don't really understand it, so please explain how to correctly initialize the core and the memory device. Thanks in advance!

[dinaabdelbaky]

Hi, I am new to the liteDRAM. I generated the core in a standalone mode, targeting Artix device, I also generated the corr. csv containing the csr addresses. I am using the core with Micron DDR3 model and a testbench to carryout some simulations and explorations of memory operations. I checked out the generated sdram_phy.h it includes init_sequence, I tried to carry out the above sequence by writing to the corresponding csr registers. However, I didn't see anything happening on the DFI interface or the memory interface. Please point out what I am missing. P.S: I have seen some similar questions, and some of the answers points out to writing data from an init file, but I don't really understand it, so please explain how to correctly initialize the core and the memory device. Thanks in advance!

[yyx32]

Hi @dinaabdelbaky ，are you generated core with gen.py script? Can you tell me how to get corr.csv and sdram_phy.h ?

[dinaabdelbaky]

Hi @yyx32 Yes, I generated the core following those steps: The addresses of the registers would be in the csv file. The sdram_phy.h is generated under "output_drisoftware\include\generated"

[dinaabdelbaky]

And I have worked out the issue I have mentioned above, the problem was not the sequence, I didn't notice that the addresses in the CSV were 32 bit wide and the wishbone interface was less wide. A simple fix to that is to take the address of the csr register in the generated csv and do right bit shifts, the amount of bit shift is equivalent 32-wishbone width.

[yyx32]

I will try it.Thanks bro.