Generate liteDRAM verilog file

[ztachip]

I am trying to generate just the DRAM controller for the Arty board using command

./gen.sh ../examples/arty.yml

But the generated verilog also contains VexRiscv.

How can I generate just the DRAM controller?

Also what is the frequency that I input to the controller, is it "input_clk_freq"? Can I change it to different clock value?

Thanks

[rowanG077]

How can I generate just the DRAM controller?

A CPU is required to perform initialization, training and calibration. You might be able to do it separately by setting cpu: None in the yaml but I don't think this path is tested.

Also what is the frequency that I input to the controller, is it "input_clk_freq"? Can I change it to different clock value?

Yes you can change it a different value. If you look inside the gen.py script you see this clock is used only as a input clock for a new PLL to be instantiated. You can use whatever frequency you like.

[ztachip]

Ok. That makes sense about the CPU (-: About the user_clk, I guess this is the clock for user AXI port? Is this clock the same as input_clk_freq? Do I have a choice on the user_clk frequency? Thx

[ztachip]

I generate the standalone litedram for Arty7 using command... gen.py ../examples/arty.yml However, I don't see how VexRiscv referenced in the generated verilog being generated. Can you help? Thx

[ztachip]

I found it. I was in the python-cpu-vexrisc. Thanks