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enjoy-digital / litedram

Small footprint and configurable DRAM core
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Avalon frontend for LiteDRAM #337

Closed hansfbaier closed 1 year ago

hansfbaier commented 1 year ago

The current implementation passes all tests except the downconverting ones. I compared with the wishbone tests and I could not find what I am missing. The wdata port just does nothing, and I can't understand why. image See the skipped tests, which are the failing ones (simulator hangs).

hansfbaier commented 1 year ago

Now all tests pass. Interestingly enough, the downconverter expects different timing of signals than the normal and upconverting ones. image

hansfbaier commented 1 year ago

The CI still fails here because it depends on https://github.com/enjoy-digital/litex/pull/1674

hansfbaier commented 1 year ago

Oh, I still forgot to account for the fact that avalon is byte addressed. What do you think would be the best way of going about this?

hansfbaier commented 1 year ago

This PR now depends on https://github.com/enjoy-digital/litex/pull/1697 and the CI should pass once that has been merged. Also the burst tests pass now. This is ready for review.

hansfbaier commented 1 year ago

Verified on the FPGA

https://youtu.be/hIuA__ascVU

hansfbaier commented 1 year ago

Litescope trace image

hansfbaier commented 1 year ago

Waitstates are quite high. 15 clock cycles :/ But using zero L2 cache at this point. Will try with 8k.

hansfbaier commented 1 year ago

Oh the glitches were probably from something else writing in scaler address space. Moved the scaler up a couple of megabytes, now the scaler video is without glitches!

hansfbaier commented 1 year ago

@enjoy-digital The CI failures do not seem to be related to the changes made here. Is the CI broken?

enjoy-digital commented 1 year ago

@hansfbaier: Good work! Will review it tomorrow. I'll also look at the CI.

enjoy-digital commented 1 year ago

Thanks @hansfbaier, this is merged. I'll fix CI if failing.