Closed hansfbaier closed 1 year ago
Ah I found out why: I need to supply enough memory cells in mem_expected
otherwise the addresses wrap around
OK tests now all pass, and it has been verified on hardware too with this design: https://github.com/MiSTeX-devel/MiSTeX-boards/blob/main/mistex_boards/qmtech_xc7a100t_daughterboard.py Which should be a downconverting one (only one SDRAM chip).
Closing this PR in favor of https://github.com/enjoy-digital/litedram/pull/340
This backports the tests from https://github.com/enjoy-digital/litedram/pull/340 to current master, to compare test results for up/downconverting bursts. After fixes of issues uncovered by the tests, the downconverter shows similar garbled memory contents in the RAM of the simulator: