LiteDRAM DDR3 Core targeting Arty AXI read data appears on the Native port instead.

enjoy-digital / litedram

Small footprint and configurable DRAM core

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LiteDRAM DDR3 Core targeting Arty AXI read data appears on the Native port instead. #344

Open dinaabdelbaky opened 10 months ago

dinaabdelbaky commented 10 months ago

Hi, I have generated LiteDRAM core targeting DDR3 with the configuration in Fig1. I have noticed for a read command issued from the AXI interface the rd_data is returned in the rd_data of native interface, not the AXI interface Fig2 axi_read

Qiange516 commented 2 months ago

@dinaabdelbaky Hello, can you read and write AXI_Litedram normally? I encountered the same type of problem as https://github.com/enjoy-digital/litedram/issues/342 （Axi port write data error #342） If it's convenient, leave an email （bumianzhe@126.com）to communicate, thank you.