Open LearnShareAlways opened 1 year ago
DE10-Lite board litex boot with sdram enabled fails on memory read/write test `litex>
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BIOS built on Sep 5 2023 00:01:20 BIOS CRC passed (c7231e8a)
LiteX git sha1: 88532150
--=============== SoC ==================-- CPU: VexRiscv @ 50MHz BUS: WISHBONE 32-bit @ 4GiB CSR: 32-bit data ROM: 128.0KiB SRAM: 8.0KiB L2: 8.0KiB SDRAM: 64.0MiB 16-bit @ 50MT/s (CL-2 CWL-2) MAIN-RAM: 64.0MiB
--========== Initialization ============-- Initializing SDRAM @0x40000000... Switching SDRAM to software control. Switching SDRAM to hardware control. Memtest at 0x40000000 (2.0MiB)... Write: 0x40000000-0x40200000 2.0MiB Read: 0x40000000-0x40200000 2.0MiB bus errors: 256/256 addr errors: 0/8192 data errors: 524288/524288 Memtest KO Memory initialization failed`
I see it is using GENSDRPHY(https://github.com/litex-hub/litex-boards/blob/master/litex_boards/targets/terasic_de10lite.py). FYI, DE10 Lite board was removed from linux-on-litex-vexriscv due to this issue (see https://github.com/litex-hub/linux-on-litex-vexriscv/issues/154)
BTW, I tried with both DM pins to active low (thought would work since there are boards with DM pins grounded ) but no luck. I am not good at memory controller but I can help on testing the fix.
DE10-Lite board litex boot with sdram enabled fails on memory read/write test `litex>
Build your hardware, easily!
(c) Copyright 2012-2023 Enjoy-Digital (c) Copyright 2007-2015 M-Labs
BIOS built on Sep 5 2023 00:01:20 BIOS CRC passed (c7231e8a)
LiteX git sha1: 88532150
--=============== SoC ==================-- CPU: VexRiscv @ 50MHz BUS: WISHBONE 32-bit @ 4GiB CSR: 32-bit data ROM: 128.0KiB SRAM: 8.0KiB L2: 8.0KiB SDRAM: 64.0MiB 16-bit @ 50MT/s (CL-2 CWL-2) MAIN-RAM: 64.0MiB
--========== Initialization ============-- Initializing SDRAM @0x40000000... Switching SDRAM to software control. Switching SDRAM to hardware control. Memtest at 0x40000000 (2.0MiB)... Write: 0x40000000-0x40200000 2.0MiB
Read: 0x40000000-0x40200000 2.0MiB
bus errors: 256/256 addr errors: 0/8192 data errors: 524288/524288 Memtest KO Memory initialization failed`
I see it is using GENSDRPHY(https://github.com/litex-hub/litex-boards/blob/master/litex_boards/targets/terasic_de10lite.py). FYI, DE10 Lite board was removed from linux-on-litex-vexriscv due to this issue (see https://github.com/litex-hub/linux-on-litex-vexriscv/issues/154)
BTW, I tried with both DM pins to active low (thought would work since there are boards with DM pins grounded ) but no luck. I am not good at memory controller but I can help on testing the fix.