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enjoy-digital / litedram

Small footprint and configurable DRAM core
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Add W9812G6JB SDRAM module #350

Closed hansfbaier closed 7 months ago

hansfbaier commented 7 months ago

Got it running at 90 MHz

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 (c) Copyright 2012-2023 Enjoy-Digital
 (c) Copyright 2007-2015 M-Labs

 BIOS built on Nov  9 2023 10:28:08
 BIOS CRC passed (7ebd4500)

 LiteX git sha1: f3f46e8c

--=============== SoC ==================--
CPU:        VexRiscv @ 90MHz
BUS:        WISHBONE 32-bit @ 4GiB
CSR:        32-bit data
ROM:        128.0KiB
SRAM:       8.0KiB
L2:     8.0KiB
SDRAM:      16.0MiB 16-bit @ 90MT/s (CL-2 CWL-2)
MAIN-RAM:   16.0MiB

--========== Initialization ============--
Initializing SDRAM @0x40000000...
Switching SDRAM to software control.
Switching SDRAM to hardware control.
Memtest at 0x40000000 (2.0MiB)...
  Write: 0x40000000-0x40200000 2.0MiB     
   Read: 0x40000000-0x40200000 2.0MiB     
Memtest OK
Memspeed at 0x40000000 (Sequential, 2.0MiB)...
  Write speed: 25.3MiB/s
   Read speed: 39.8MiB/s

--============== Boot ==================--
Booting from serial...
Press Q or ESC to abort boot completely.
sL5DdSMmkekro
             Timeout
No boot medium found

--============= Console ================--
enjoy-digital commented 7 months ago

Thanks @hansfbaier, that's merged.