Wishbone port does not accept more than one operation despite cmd_buffer_depth non-null in LiteDram yaml file,

[fontamsoc]

In my LiteDram yaml file, I am using Wishbone user port as follow:

"user_ports": {
    "wishbone_0" : {
        "type": "wishbone",
    },
},

The generated Wishbone port does not have a stall signal, and asserting the stb signal more than once without waiting for the corresponding ack signal assertion, causes ack signal to never get asserted.

I have cmd_buffer_depth in the LiteDram yaml as follow:

"cmd_buffer_depth": 16, # Depth of the command buffer

Isn't the cmd_buffer_depth in LiteDram yaml file meant to allow more than one operation without waiting for the ack signal assertion ?