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enjoy-digital / litedram

Small footprint and configurable DRAM core
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litedram/address_mapping Add bank_byte_alignment #360

Closed Dolu1990 closed 3 months ago

Dolu1990 commented 4 months ago

This PR add ControllerSettings.bank_byte_alignment which allow to specifiy how many byte (minimum) there should be between bank address change.

This allow to align it to L2 cache sets size, which improve performances quite a bit on VexiiRiscv : VexiiRiscv RV64GC with hadware prefetch, 256KB 4way L2, running at 100 Mhz => 

without this PR
  Write speed: 197.1MiB/s
   Read speed: 379.4MiB/s 

With this PR and 
            self.add_sdram("sdram",
                phy           = self.ddrphy,
                module        = MT41K256M16(sys_clk_freq, "1:4"),
                l2_cache_size = kwargs.get("l2_size", 8192),
               controller_settings=ControllerSettings(bank_byte_alignment= 256*1024//4) # <-----
            )
  Write speed: 252.3MiB/s
   Read speed: 424.6MiB/s

When set to 0 (default value) it will not interfer with the previous behaviour of address_mapping = "ROW_BANK_COL",

enjoy-digital commented 3 months ago

Thanks @Dolu1990!