Generation fails because of wrong type of master and slave?

For simplicity, let's use the standalone generator:

$ ./gen.py arty.yml 
INFO:SoC:        __   _ __      _  __  
INFO:SoC:       / /  (_) /____ | |/_/  
INFO:SoC:      / /__/ / __/ -_)>  <    
INFO:SoC:     /____/_/\__/\__/_/|_|  
INFO:SoC:  Build your hardware, easily!
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoC:Creating SoC... (2022-06-16 16:57:15)
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoC:FPGA device : .
INFO:SoC:System clock: 100.00MHz.
INFO:SoCBusHandler:Creating Bus Handler...
INFO:SoCBusHandler:32-bit wishbone Bus, 4.0GiB Address Space.
INFO:SoCBusHandler:Adding reserved Bus Regions...
INFO:SoCBusHandler:Bus Handler created.
INFO:SoCCSRHandler:Creating CSR Handler...
INFO:SoCCSRHandler:8-bit CSR Bus, 32-bit Aligned, 16.0KiB Address Space, 2048B Paging (Up to 32 Locations).
INFO:SoCCSRHandler:Adding reserved CSRs...
INFO:SoCCSRHandler:CSR Handler created.
INFO:SoCIRQHandler:Creating IRQ Handler...
INFO:SoCIRQHandler:IRQ Handler (up to 32 Locations).
INFO:SoCIRQHandler:Adding reserved IRQs...
INFO:SoCIRQHandler:IRQ Handler created.
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoC:Initial SoC:
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoC:32-bit wishbone Bus, 4.0GiB Address Space.
INFO:SoC:8-bit CSR Bus, 32-bit Aligned, 16.0KiB Address Space, 2048B Paging (Up to 32 Locations).
INFO:SoC:IRQ Handler (up to 32 Locations).
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoCCSRHandler:ctrl CSR allocated at Location 0.
INFO:SoCBusHandler:io0 Region added at Origin: 0x00000000, Size: 0x100000000, Mode: RW, Cached: False Linker: False.
INFO:SoCBusHandler:csr Region added at Origin: 0x00000000, Size: 0x00010000, Mode: RW, Cached: False Linker: False.
INFO:SoCBusHandler:csr added as Bus Slave.
INFO:SoCCSRHandler:bridge added as CSR Master.
INFO:SoCCSRHandler:ethphy CSR allocated at Location 1.
INFO:SoCBusHandler:ethmac Region added at Origin: 0x00010000, Size: 0x00002000, Mode: RW, Cached: False Linker: False.
INFO:SoCCSRHandler:ethmac CSR allocated at Location 2.
Traceback (most recent call last):
  File "/home/boris/LX/liteeth/liteeth/./gen.py", line 346, in <module>
    main()
  File "/home/boris/LX/liteeth/liteeth/./gen.py", line 331, in main
    soc = MACCore(platform, core_config)
  File "/home/boris/LX/liteeth/liteeth/./gen.py", line 244, in __init__
    self.add_wb_master(bridge.wishbone)
  File "/home/boris/LX/litex/litex/soc/integration/soc_core.py", line 203, in add_wb_master
    self.bus.add_master(master=wbm)
  File "/home/boris/LX/litex/litex/soc/integration/soc.py", line 346, in add_master
    master = self.add_adapter(name, master, "m2s")
  File "/home/boris/LX/litex/litex/soc/integration/soc.py", line 315, in add_adapter
    bridge_cls = {
KeyError: (<class 'migen.genlib.record.Record'>, <class 'litex.soc.interconnect.wishbone.Interface'>)

To debug, I put a breakpoint in add_adapter():

bridge_cls = {
   (wishbone.Interface, axi.AXILiteInterface): axi.Wishbone2AXILite,
   (axi.AXILiteInterface, wishbone.Interface): axi.AXILite2Wishbone,
}[type(master), type(slave)]

This blows up because the master is a migen.genlib.record.Record, and the slave is a litex.soc.interconnect.wishbone.Interface.

Is this perhaps some kind of incompatibility between versions of LiteEth and LiteX API?

enjoy-digital / liteeth

Generation fails because of wrong type of master and slave? #113