Closed ratzupaltuff closed 12 months ago
I'm not experienced with Xilinx but from looking at their site the ZCU104 is an UltraScale+ part. So it seems you require the usrgmii Phy not the s7rgmii
you used.
Hi, Thank you for your answer! I overlooked the usrgmii Phy completely, my bad. I used it now and adapted my files a bit:
litex_boards/targets/xilinx_zcu104.py:
from liteeth.phy.usrgmii import LiteEthPHYRGMII
...
# Ethernet ---------------------------------------------------------------------------------
if with_ethernet:
# RGMII Ethernet PHY -------------------------------------------------------------------
self.ethphy = LiteEthPHYRGMII(
clock_pads = self.platform.request("eth_clocks"),
pads = self.platform.request("eth"),
rx_delay=1e-9,
tx_delay=1e-9,
usp=True)
# Change ref clk for IDELAYE3 - Copied from avnet_aesku40
for special in self.ethphy.rx._fragment.specials:
if special.name_override == "IDELAYE3":
for item in special.items:
if item.name == "REFCLK_FREQUENCY":
item.value=500.00
self.add_ethernet(phy=self.ethphy)
litex_boards/platforms/xilinx_zcu104.py:
# Ethernet
("eth_clocks", 0,
Subsignal("tx", Pins("J31")),
Subsignal("rx", Pins("K31")),
IOStandard("LVCMOS18")
),
("eth", 0,
Subsignal("rx_ctl", Pins("L30")),
Subsignal("rx_data", Pins("K32 K33 K34 L29")),
Subsignal("tx_ctl", Pins("K30")),
Subsignal("tx_data", Pins("J32 J34 K28 K29")),
# Subsignal("rst_n", Pins("P06")), #dont know what port to use
Subsignal("mdc", Pins("L33")),
Subsignal("mdio", Pins("L34")),
IOStandard("LVCMOS18"),
),
I get the following errors:
Start Applying XDC Timing Constraints
---------------------------------------------------------------------------------
CRITICAL WARNING: [Synth 8-3321] create_clock attempting to set clock on an unknown port/pin for constraint at line 841 of /home/XXX/build/zcu104/gateware/zcu104.xdc. [/home/XXX/build/zcu104/gateware/zcu104.xdc:841]
CRITICAL WARNING: [Synth 8-3321] create_clock attempting to set clock on an unknown port/pin for constraint at line 843 of /home/XXX/build/zcu104/gateware/zcu104.xdc. [/home/XXX/build/zcu104/gateware/zcu104.xdc:843]
...
Parsing XDC File [/home/XXX/build/zcu104/gateware/zcu104.xdc]
CRITICAL WARNING: [Vivado 12-1411] Cannot set LOC property of ports, Could not legally place terminal eth_clocks_tx at N29 (PS8_X0Y0) since it belongs to a shape containing instance ODDRE1. The shape requires relative placement between eth_clocks_tx and ODDRE1 that can not be honoured because it would result in an invalid location for ODDRE1. [/home/XXX/build/zcu104/gateware/zcu104.xdc:769]
CRITICAL WARNING: [Vivado 12-1411] Cannot set LOC property of ports, Site location (PS8_X0Y0) is not valid for the shape with the following elements:
IBUF/INBUF_INST
eth_clocks_rx
IBUF/IBUFCTRL_INST
[/home/XXX/build/zcu104/gateware/zcu104.xdc:773]
CRITICAL WARNING: [Vivado 12-1411] Cannot set LOC property of ports, Could not legally place terminal eth_rx_ctl at N29 (PS8_X0Y0) since it belongs to a shape containing instance IDDRE1. The shape requires relative placement between eth_rx_ctl and IDDRE1 that can not be honoured because it would result in an invalid location for IDDRE1. [/home/XXX/build/zcu104/gateware/zcu104.xdc:777]
CRITICAL WARNING: [Vivado 12-1411] Cannot set LOC property of ports, Could not legally place terminal eth_rx_data[0] at N29 (PS8_X0Y0) since it belongs to a shape containing instance IDDRE1_1. The shape requires relative placement between eth_rx_data[0] and IDDRE1_1 that can not be honoured because it would result in an invalid location for IDDRE1_1. [/home/XXX/build/zcu104/gateware/zcu104.xdc:781]
CRITICAL WARNING: [Vivado 12-1411] Cannot set LOC property of ports, Could not legally place terminal eth_rx_data[1] at N29 (PS8_X0Y0) since it belongs to a shape containing instance IDDRE1_2. The shape requires relative placement between eth_rx_data[1] and IDDRE1_2 that can not be honoured because it would result in an invalid location for IDDRE1_2. [/home/XXX/build/zcu104/gateware/zcu104.xdc:785]
...
CRITICAL WARNING: [Vivado 12-1411] Cannot set LOC property of ports, Site location (PS8_X0Y0) is not valid for the shape with the following elements:
eth_mdc_OBUF_inst
eth_mdc
[/home/XXX/build/zcu104/gateware/zcu104.xdc:817]
CRITICAL WARNING: [Vivado 12-1411] Cannot set LOC property of ports, Site location (PS8_X0Y0) is not valid for the shape with the following elements:
eth_mdio_IOBUF_inst/INBUF_INST
eth_mdio_IOBUF_inst/OBUFT
eth_mdio
eth_mdio_IOBUF_inst/IBUFCTRL_INST
[/home/XXX/build/zcu104/gateware/zcu104.xdc:821]
...
ERROR: [DRC UCIO-1] Unconstrained Logical Port: 14 out of 134 logical ports have no user assigned specific location constraint (LOC). This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all pin locations. This design will fail to generate a bitstream unless all logical ports have a user specified site LOC constraint defined. To allow bitstream creation with unspecified pin locations (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks UCIO-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: eth_rx_data[3:0], eth_tx_data[3:0], eth_clocks_rx, eth_clocks_tx, eth_mdc, eth_mdio, eth_rx_ctl, and eth_tx_ctl.
WARNING: [DRC BUFC-1] Input Buffer Connections: Input buffer IOBUFDSE3/IBUFCTRL_INST has no loads. It is recommended to have an input buffer drive an internal load.
...
INFO: [Vivado 12-3199] DRC finished with 1 Errors, 19 Warnings
INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information.
ERROR: [Vivado 12-1345] Error(s) found during DRC. Bitgen not run.
INFO: [Common 17-83] Releasing license: Implementation
6 Infos, 19 Warnings, 0 Critical Warnings and 2 Errors encountered.
write_bitstream failed
write_bitstream: Time (s): cpu = 00:00:13 ; elapsed = 00:00:07 . Memory (MB): peak = 4465.363 ; gain = 0.000 ; free physical = 449 ; free virtual = 8185
ERROR: [Common 17-39] 'write_bitstream' failed due to earlier errors.
Can someone give me a hint what the problem may be or even how to solve it?
Oke this is going in the right direction!
It seems it's not taking the pin locations constraints properly. Does litex generate the proper XDC file here? Did you load it into the tooling? Are you sure the locations you specified are good?
Beyond this I can't really help.
ZCU 104 is a zynqmp SoC Ultrascale+ (ie FPGA+CPU). Ethernet port is connected to PS (CPU) side. PL (FPGA) can't access to these pins.
Ah, thank you! I think I missed that in the manual. I will use a different board then.
Hi, i am trying to add Ethernet to the ZCU104 Board.
So far I added the following: litex_boards/targets/xilinx_zcu104.py:
litex_boards/platforms/xilinx_zcu104.py:
But if I run the build I get Errors:
When I rename ODDR -> ODDRE1 IDELAYE2 -> IDELAYE3 IDDR -> IDDRE1 in liteeth/phy/s7rgmii.py I get a different error:
I am new to Litex and FPGA programming with Vivado. Can someone help me, what the error means and what needs to be done to resolve it? Is there another liteeth-phy that is working with the zcu104?