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enjoy-digital / liteeth

Small footprint and configurable Ethernet core
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ecp5rgmii does not meet timing closure #47

Closed festlv closed 4 years ago

festlv commented 4 years ago

I am trying to build versa_ecp5.py target from litex-boards with Ethernet support, using trellis toolchain. litex/litex-boards/litex_boards/targets$ ./versa_ecp5.py --build --with-ethernet --integrated-rom-size 36864 (enlarging the ROM size was required because it overflows the default 32K).

The particular clock which fails is:

Info: Critical path report for clock '$glbnet$eth_clocks_rx$TRELLIS_IO_IN' (posedge -> posedge): Info: curr total Info: 0.3 0.3 Source main_ethmac_tx_cdc_graycounter1_q_next_binary_TRELLIS_FF_DI_2_SLICE.Q0 Info: 1.0 1.3 Net main_ethmac_tx_cdc_graycounter1_q_next_binary_TRELLIS_FF_DI_Q[1] budget 0.719000 ns (55,41) -> (52,40) Info: Sink storage_11.3.1.0$DPRAM1_SLICE.B1 Info: 0.1 1.4 Source storage_11.3.1.0$DPRAM1_SLICE.F1 Info: 0.8 2.3 Net storage_11.3.0.0_DO[7] budget 0.719000 ns (52,40) -> (52,39) Info: Sink storage_11.3.3.0_DO_LUT4_A_C_LUT4_Z_SLICE.C1 Info: 0.1 2.4 Source storage_11.3.3.0_DO_LUT4_A_C_LUT4_Z_SLICE.F1 Info: 0.3 2.7 Net storage_11.3.3.0_DO_LUT4_A_C_LUT4_Z_D[2] budget 0.719000 ns (52,39) -> (52,39) Info: Sink storage_11.3.3.0_DO_LUT4_A_C_LUT4_Z_SLICE.D0 Info: 0.1 2.8 Source storage_11.3.3.0_DO_LUT4_A_C_LUT4_Z_SLICE.F0 Info: 0.7 3.6 Net storage_11.3.3.0_DO_LUT4_A_C[2] budget 0.718000 ns (52,39) -> (57,37) Info: Sink storage_11.2.3.0_DO_LUT4_A_D_LUT4_Z_SLICE.D1 Info: 0.1 3.7 Source storage_11.2.3.0_DO_LUT4_A_D_LUT4_Z_SLICE.F1 Info: 0.4 4.1 Net storage_11.3.3.0_DO_LUT4_A_Z[1] budget 0.718000 ns (57,37) -> (57,37) Info: Sink storage_11.3.3.0_DO_LUT4_A_Z_LUT4_A_SLICE.C0 Info: 0.1 4.3 Source storage_11.3.3.0_DO_LUT4_A_Z_LUT4_A_SLICE.F0 Info: 0.8 5.1 Net main_ethphy_sink_payload_data_LUT4_Z_7_B_LUT4_C_Z[3] budget 5.031000 ns (57,37) -> (62,37) Info: Sink main_ethphy_sink_payload_data_LUT4_Z_A_PFUMX_Z_SLICE.M0 Info: 0.2 5.2 Source main_ethphy_sink_payload_data_LUT4_Z_A_PFUMX_Z_SLICE.OFX0 Info: 0.7 6.0 Net main_ethphy_sink_payload_data_LUT4_Z_A[0] budget 5.031000 ns (62,37) -> (64,38) Info: Sink builder_subfragments_liteethmacpreambleinserter_next_state_LUT4_Z_SLICE.A1 Info: 0.1 6.1 Source builder_subfragments_liteethmacpreambleinserter_next_state_LUT4_Z_SLICE.F1 Info: 2.2 8.4 Net main_ethmac_tx_gap_inserter_source_payload_data[7] budget 5.031000 ns (64,38) -> (90,62) Info: Sink eth_tx_data[3]$tr_io$IOL.TXDATA1 Info: 0.1 8.5 Setup eth_tx_data[3]$tr_io$IOL.TXDATA1 Info: 1.4 ns logic, 7.1 ns routing

Warning: Max frequency for clock '$glbnet$eth_clocks_rx$TRELLIS_IO_IN': 118.25 MHz (FAIL at 125.00 MHz)

Versions: yosys: 12132b6850747aec99715fdfa3184fe3ebefa015 trellis: 8c0a6382e11b160ed88d17af8493c12a897617ed nextpnr: c8ecb8341ca766e1e7565cc2b652b63eaba67508 litex-boards: 63b65e278c279a9cf8c4da31db8f7e845edba394 liteeth: 54acf9fd76c226d7760294ffde86418e52e0951b

enjoy-digital commented 4 years ago

I would need to double check, but since it's on the graycounter of the AsyncFIFO, it should probably be a defined as a False path (so you can ignore it), but it's not yet possible to define False paths with Nextpnr.